Voltage conversion circuit and memory

Patent metadata

Field	Value
Publication number	US-12301237-B2
Application number	US-202318157155-A
Country	US
Kind code	B2
Filing date	Jan 20, 2023
Priority date	Jul 16, 2021
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A voltage conversion circuit and a memory are provided. The voltage conversion circuit includes a driving circuit and a receiving circuit. The driving circuit is powered by a first voltage, and outputs a first signal at an output end, a voltage of a high level of the first signal being less than the first voltage. The receiving circuit is powered by the first voltage, receives the first signal at a first input end, and receives a sampling signal at a second input end. The receiving circuit is configured to output a second signal according to the sampling signal, and a voltage of a high level of the second signal is equal to the first voltage.

First claim

The invention claimed is:

1. A voltage conversion circuit, comprising:
a driving circuit, powered by a first voltage, and outputting a first signal at an output end, a voltage of a high level of the first signal being less than the first voltage; and
a receiving circuit, powered by the first voltage, receiving the first signal at a first input end, and receiving a sampling signal at a second input end, wherein the receiving circuit is configured to output a second signal according to the sampling signal, and a voltage of a high level of the second signal is equal to the first voltage;
wherein the receiving circuit comprises:
a first P-type transistor, a gate of the first P-type transistor being connected to the first input end and a source of the first P-type transistor being connected to the first voltage;
a second P-type transistor, a gate of the second P-type transistor being electrically connected to the second input end through a first inverter, and a source of the second P-type transistor being connected to a drain of the first P-type transistor;
a first N-type transistor, a gate of the first N-type transistor being connected to the first input end and a source of the first N-type transistor being grounded; and
a second N-type transistor, a gate of the second N-type transistor being electrically connected to the second input end, a source of the second N-type transistor being connected to a drain of the first N-type transistor, and a drain of the second N-type transistor being connected to a drain of the second P-type transistor;
wherein the drain of the second N-type transistor is an output end of the receiving circuit.

2. The voltage conversion circuit of claim 1 , further comprising:
a latch circuit, an input end of the latch circuit receiving the second signal, and the latch circuit being configured to latch the second signal.

3. The voltage conversion circuit of claim 2 , wherein the latch circuit comprises:
a second inverter, an input end of the second inverter being connected to an output end of the receiving circuit, and an output end of the second inverter being connected to an output end of the latch circuit; and
a third inverter, an input end of the third inverter being connected to the output end of the latch circuit, and an output end of the third inverter being connected to the input end of the second inverter.

4. The voltage conversion circuit of claim 3 , wherein the third inverter is in a closed state in response to that the sampling signal is in an enabled state.

5. The voltage conversion circuit of claim 1 , wherein an enable level of the sampling signal occurs within a preset time in which a level of the first signal is changed.

6. The voltage conversion circuit of claim 5 , wherein the enable level of the sampling signal is maintained for less than half of time for which the first signal is at a high level.

7. The voltage conversion circuit of claim 1 , wherein the sampling signal is a pulse signal with a set period.

8. The voltage conversion circuit of claim 7 , wherein a duty cycle of an enable level of the sampling signal is less than ½.

9. The voltage conversion circuit of claim 1 , wherein the voltage of the high level of the first signal causes a pull-up capability of the first P-type transistor to be greater than a pull-down capability of the first N-type transistor.

10. The voltage conversion circuit of claim 1 , wherein a difference between the first voltage and the voltage of the high level of the first signal is less than or equal to a threshold voltage of the first P-type transistor.

11. The voltage conversion circuit of claim 1 , wherein the driving circuit comprises:
a third N-type transistor and a fourth N-type transistor, a drain of the third N-type transistor being connected to the first voltage, a source of the third N-type transistor being connected to a drain of the fourth N-type transistor, a source of the fourth N-type transistor being grounded, and the drain of the fourth N-type transistor being served as the output end of the driving circuit.

12. The voltage conversion circuit of claim 11 , wherein the third N-type transistor receives a first control signal at a gate and the fourth N-type transistor receives a second control signal at a gate, the first control signal having an opposite phase to the second control signal.

13. The voltage conversion circuit of claim 12 , wherein the third N-type transistor has a same size as the fourth N-type transistor.

14. A memory, comprising the voltage conversion circuit of claim 1 .

15. A voltage conversion circuit, comprising:
a driving circuit, powered by a first voltage, and outputting a first signal at an output end, a voltage of a high level of the first signal being less than the first voltage; and
a receiving circuit, powered by the first voltage, receiving the first signal at a first input end, and receiving a sampling signal at a second input end, wherein the receiving circuit is configured to output a second signal according to the sampling signal, and a voltage of a high level of the second signal is equal to the first voltage;
wherein the driving circuit comprises:
a first N-type transistor and a second N-type transistor, a drain of the first N-type transistor being directly connected to the first voltage, a source of the first N-type transistor being connected to a drain of the second N-type transistor, a source of the second N-type transistor being grounded, and the drain of the second N-type transistor being served as the output end of the driving circuit.

16. The voltage conversion circuit of claim 15 , wherein the first N-type transistor receives a first control signal at a gate and the second N-type transistor receives a second control signal at a gate, the first control signal having an opposite phase to the second control signal.

17. The voltage conversion circuit of claim 16 , wherein the first N-type transistor has a same size as the second N-type transistor.

18. A memory, comprising the voltage conversion circuit of claim 15 .

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Kangling

Classifications

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C11/40

  using transistors · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title