Array base plate and method for manufacturing the same, display panel

Patent metadata

Field	Value
Publication number	US-12300704-B2
Application number	US-202218027248-A
Country	US
Kind code	B2
Filing date	Apr 26, 2022
Priority date	Apr 26, 2022
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

The present application provides an array base plate and a method for manufacturing the same, a display panel, the array base plate including a substrate; a first conducting layer located at one side of the substrate, and including a plurality of data lines arranged in an array; a second conducting layer located at one side of the first conducting layer away from the substrate, and in direct contact with a part of a region of the first conducting layer, and including a pixel electrode and a compensating electrode; wherein an orthographic projection of the compensating electrode on the substrate is located within orthographic projections of the data lines on the substrate. The embodiments of the present application provide an array base plate with low cost, high preparation yield, and good reliability.

First claim

The invention claimed is:

1. An array base plate, comprising:
a substrate;
a first conducting layer located at one side of the substrate, and comprising a plurality of data lines arranged in an array;
a second conducting layer located at one side of the first conducting layer away from the substrate, and in direct contact with a part of a region of the first conducting layer, and comprising a pixel electrode and a compensating electrode;
wherein an orthographic projection of the compensating electrode on the substrate is located within orthographic projections of the data lines on the substrate;
wherein the array base plate further comprises a third conducting layer located between the first conducting layer and the substrate; and the third conducting layer comprises a plurality of gate lines arranged in an array, and the gate lines intersect and are insulated with the data lines;
wherein the array base plate further comprises transistor, and the first conducting layer further comprises a first electrode of the transistor and a second electrode of the transistor, and the pixel electrode is in direct contact with a part of a region of the first electrode of the transistor, and the data lines are connected to the second electrode of the transistor;
wherein the first electrode of the transistor comprises a first portion parallel to an extending direction of each of the gate lines, a second portion parallel to an extending direction of each of the gate lines, and a connecting portion connecting the first portion and the second portion; and
a minimum distance between the second portion and the each of the gate lines is larger than a minimum distance between the first portion and the each of the gate lines, and the pixel electrode covers the second portion and a part of the connecting portion.

2. The array base plate according to claim 1 , wherein an extending direction of the compensating electrode and an extending direction of each of the data lines are the same, and in the extending direction of the each of the data lines, a length of the compensating electrode is less than or equal to a length of the each of the data lines.

3. The array base plate according to claim 1 , wherein in a direction perpendicular to an extending direction of the data lines, sizes of the orthographic projections of the data lines on the substrate are larger than or equal to a size of the orthographic projection of the compensating electrode on the substrate.

4. The array base plate according to claim 1 , wherein
a part of each of the data lines located between two adjacent gate lines comprises a first line segment, a bending part, and a second line segment connected sequentially; and the compensating electrode covers at least a part of regions of the first line segment and the second line segment.

5. The array base plate according to claim 4 , wherein the each of the data lines further comprise a third line segment and a fourth line segment, and the third line segment is connected to an end of the first line segment away from the bending part; the fourth line segment is connected to an end of the second line segment away from the bending part; an orthographic projection of the third line segment on the substrate and an orthographic projection of the fourth line segment on the substrate overlap with orthographic projections of the gate lines on the substrate, respectively;
wherein the compensating electrode covers at least a part of regions of the third line segment and the fourth line segment.

6. The array base plate according to claim 5 , wherein the compensating electrode covers the first line segment, the second line segment, the third line segment and the fourth line segment.

7. The array base plate according to claim 5 , wherein a width of the third line segment along a direction perpendicular to an extending direction of the third line segment is larger than a width of the first line segment along a direction perpendicular to an extending direction of the first line segment; a width of the fourth line segment along a direction perpendicular to an extending direction of the fourth line segment is larger than a width of the second line segment along a direction perpendicular to an extending direction of the second line segment.

8. The array base plate according to claim 7 , wherein a width of a part of the compensating electrode covering the third line segment along the direction perpendicular to the extending direction of the third line segment is larger than a width of a part of the compensating electrode covering a main structure of the first line segment along the direction perpendicular to the extending direction of the first line segment; and
a width of a part of the compensating electrode covering the fourth line segment along the direction perpendicular to the extending direction of the fourth line segment is larger than a width of a part of the compensating electrode covering a main structure of the second line segment along the direction perpendicular to the extending direction of the second line segment.

9. The array base plate according to claim 4 , wherein the pixel electrode is located at a position defined by two adjacent data lines and two adjacent gate lines, and the minimum distance between the pixel electrode and the compensating electrode is larger than or equal to 5 μm.

10. An array base plate, comprising:
a substrate;
a first conducting layer located at one side of the substrate, and comprising a plurality of data lines arranged in an array;
a second conducting layer located at one side of the first conducting layer away from the substrate, and in direct contact with a part of a region of the first conducting layer, and comprising a pixel electrode and a compensating electrode;
wherein an orthographic projection of the compensating electrode on the substrate is located within orthographic projections of the data lines on the substrate;
wherein the array base plate further comprises a third conducting layer located between the first conducting layer and the substrate; the third conducting layer comprises a plurality of gate lines arranged in an array, and the gate lines intersect and are insulated with the data lines; and
a part of each of the data lines located between two adjacent gate lines comprises a first line segment, a bending part, and a second line segment connected sequentially; and the compensating electrode covers at least a part of regions of the first line segment and the second line segment;
wherein the array base plate further comprises transistor, and the first conducting layer further comprises a first electrode of the transistor and a second electrode of the transistor, and the pixel electrode is in direct contact with a part of a region of the first electrode of the transistor, and the data lines are connected to the second electrode of the transistor;
wherein the array base plate further comprises a semiconductor layer located between the first conducting layer and the third conducting layer, a part of a region of the semiconductor layer is in direct contact with the first conducting layer; and
the semiconductor layer comprises a first active portion, the orthographic projection of the compensating electrode on the substrate is located within an orthographic projection of the first active portion on the substrate, and the orthographic projections of the data lines on the substrate are located within the orthographic projection of the first active portion on the substrate.

11. The array base plate according to claim 10 , wherein the semiconductor layer further comprises a second active portion, the first active portion and the second active portion are connected, an

Assignees

• Beijing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wang Desheng
• Feng Dawei
• Yang Zhichao
• Wang Jian
• Zhang Yong
• Li Hui
• Deng Qi
• Nie Lingfang
• Hao Longhu
• Guo Zanwu

Classifications

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• G02F1/1368 Primary

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136209

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title