Semiconductor device and semiconductor circuit

Patent metadata

Field	Value
Publication number	US-12300695-B2
Application number	US-202117473579-A
Country	US
Kind code	B2
Filing date	Sep 13, 2021
Priority date	Mar 12, 2021
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A semiconductor device of embodiments includes: a semiconductor layer including a first trench, a second trench, a first semiconductor region of a first conductive type, a second semiconductor region of a second conductive type provided between a first face and the first semiconductor region, between the first trench and the second trench, and in contact with the second trench, a third semiconductor region of a first conductive type provided between the first trench and the second semiconductor region, a fourth semiconductor region of a second conductive type provided between the third semiconductor region and the first face, and a fifth semiconductor region of a second conductive type provided between the second semiconductor region and the first face, spaced from the fourth semiconductor region, in contact with the second trench; a first electrode on a first face side; and a second electrode on a second face side.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor layer having a first face and a second face opposite to the first face and including:
a first trench provided in a first face side;
a second trench provided in a first face side;
a first semiconductor region of a first conductive type in contact with the first trench and the second trench;
a second semiconductor region of a second conductive type provided between the first face and the first semiconductor region, the second semiconductor region provided between the first trench and the second trench, and the second semiconductor region being physically in contact with the second trench;
a third semiconductor region of a first conductive type provided between the first semiconductor region and the first face, the third semiconductor region provided between the first trench and the second semiconductor region, the third semiconductor region being in contact with the first trench, the third semiconductor region being separated from the second trench, the third semiconductor region being in contact with the second semiconductor region, and the third semiconductor region being physically in contact with the first semiconductor region;
a fourth semiconductor region of a second conductive type provided between the third semiconductor region and the first face, the fourth semiconductor region provided between the first trench and the second semiconductor region, the fourth semiconductor region being physically in contact with the first trench, the fourth semiconductor region being physically in contact with the second semiconductor region, the fourth semiconductor region being physically in contact with the third semiconductor region, and the fourth semiconductor region having a second conductive type impurity concentration higher than a second conductive type impurity concentration in the second semiconductor region; and
a fifth semiconductor region of a second conductive type provided between the second semiconductor region and the first face, the fifth semiconductor region being physically in contact with the second trench, and the fifth semiconductor region having a second conductive type impurity concentration higher than the second conductive type impurity concentration in the second semiconductor region, and the second semiconductor region being provided between the fourth semiconductor region and the fifth semiconductor region;

a first electrode provided on the first face side of the semiconductor layer and in contact with the second semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; and
a second electrode provided on a second face side of the semiconductor layer,
wherein a distance between the first trench and the second trench is larger than a depth of the first trench.

2. The semiconductor device according to claim 1 ,
wherein a first conductive type impurity concentration in the third semiconductor region is higher than a first conductive type impurity concentration in the first semiconductor region.

3. The semiconductor device according to claim 1 ,
wherein a material of a first portion of the first electrode in contact with the second semiconductor region is different from a material of a second portion of the first electrode in contact with the fourth semiconductor region.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Matsudai Tomoko
• Iwakaji Yoko
• Itokazu Hiroko

Classifications

• H10D62/109

  Reduced surface field [RESURF] PN junction structures · CPC title

• H10D12/481

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10D8/50

  PIN diodes · CPC title

• H03K17/08128

  in composite switches · CPC title

• H10D62/129

  Cathode regions of diodes · CPC title