Memory repair system and method

Patent metadata

Field	Value
Publication number	US-12300337-B2
Application number	US-202217944691-A
Country	US
Kind code	B2
Filing date	Sep 14, 2022
Priority date	Sep 14, 2022
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A system for repairing a random access memory may include serial test interface logic, fuse-sense logic, a repair data register chain, and multiplexing logic. The repair data register chain may include serially interconnected data registers configured to shift data through the repair data register chain. Each data register of the repair data register chain may have a data output configured to be coupled to a repair information input of the random access memory. The multiplexing logic may be configured to provide a soft-repair mode and a hard-repair mode. When the soft-repair mode is selected, the multiplexing logic may be configured to receive soft-repair data provided by the serial test interface logic into the data registers. When the hard-repair mode is selected, the multiplexing logic may be configured to receive the data provided by the fuse-sense logic into the data registers.

First claim

What is claimed is:

1. A system for repairing a random access memory, comprising:
serial test interface logic;
fuse-sense logic;
a repair data register chain comprising a plurality of serially interconnected data registers configured to shift data serially through the repair data register chain, each data register of the repair data register chain having a data output configured to be coupled to a repair information input of the random access memory;
multiplexing logic configured to provide a soft-repair mode and a hard-repair mode, the multiplexing logic configured to selectably receive into the data registers soft-repair data provided by the serial test interface logic when the soft-repair mode is selected or hard-repair data provided by the fuse-sense logic when the hard-repair mode is selected;

a control signal register chain comprising a plurality of serially interconnected control signal registers configured to shift data serially through the control signal register chain, an input of the control signal register chain coupled to a serial data output of the serial test interface logic, an output of each control signal register coupled to control inputs of the multiplexing logic; and
a control signal register chain comprising a plurality of serially interconnected control signal registers configured to shift data serially through the control signal register chain, an input of the control signal register chain coupled to a serial data output of the serial test interface logic, an output of each control signal register coupled to control inputs of the multiplexing logic.

2. The system of claim 1 , wherein the serial test interface logic comprises Joint Test Action Group (JTAG) logic.

3. The system of claim 1 , wherein the multiplexing logic comprises a first plurality of multiplexers corresponding to the plurality of data registers, each multiplexer of the first plurality of multiplexers having an output coupled to a data input of the corresponding data register, each multiplexer of the first plurality of multiplexers having a first input configured to receive a portion of the hard-repair data provided by the fuse-sense logic and a second input configured to receive a portion of the soft-repair data.

4. The system of claim 3 , wherein the second input of a first multiplexer of the first plurality of multiplexers is coupled to a serial data output of the serial test interface logic, and the second input of each other multiplexer of the first plurality of multiplexers is coupled to the data output of one of the data registers.

5. The system of claim 4 , further comprising a second plurality of multiplexers corresponding to the plurality of data registers, a first input of each multiplexer of the second plurality of multiplexers coupled to the fuse-sense logic, a second input of each multiplexer of the second plurality of multiplexers coupled to the data output of the corresponding data register, and an output of each multiplexer of the second plurality of multiplexers coupled to the first input of a multiplexer of the first plurality of multiplexers.

6. The system of claim 1 , further comprising a clock multiplexer configured to selectably couple to a clock input of each data register a serial test interface clock signal when the soft-repair mode is selected or a functional clock signal when the hard-repair mode is selected.

7. The system of claim 1 , wherein the serial test interface logic, the fuse-sense logic, the repair data register chain, and the multiplexing logic are included in a system-on-a-chip (SoC).

8. A system for repairing a random access memory, comprising:
means for receiving a mode selection signal indicating a soft-repair mode or a hard-repair mode;
means for reading soft-repair data from serial test interface logic into a repair data register chain via multiplexing logic in response to the mode selection signal indicating the soft-repair mode, the repair data register chain comprising a plurality of serially interconnected data registers;
means for reading hard-repair data from fuse-sense logic into the repair data register chain via the multiplexing logic in response to the mode selection signal indicating the hard-repair mode;
means for providing repair information from outputs of the data registers to a repair information input of the random access memory;
means for transferring data serially from the serial test interface logic into a control signal register chain comprising a plurality of serially interconnected control signal registers; and
means for coupling outputs of the control signal registers to control inputs of the multiplexing logic.

9. The system of claim 8 , wherein the serial test interface logic comprises Joint Test Action Group (JTAG) logic.

10. The system of claim 8 , wherein:
The means for reading hard-repair data comprises means for providing a portion of the hard-repair data to a first input of each multiplexer of a first plurality of multiplexers corresponding to the plurality of data registers; and
The means for reading soft-repair data comprises means for providing a portion of the soft-repair data to a second input of each multiplexer of the first plurality of multiplexers.

11. The system of claim 10 , wherein the means for providing the portion of the soft-repair data comprises:
means for coupling a serial data output of the serial test interface logic to the second input of a first multiplexer of the first plurality of multiplexers; and
means for coupling outputs of the data registers to the second input of each other multiplexer of the first plurality of multiplexers.

12. The system of claim 11 , further comprising:
means for coupling a first input of each multiplexer of a second plurality of multiplexers to the fuse-sense logic, the second plurality of multiplexers corresponding to the plurality of data registers; and
means for coupling a second input of each multiplexer of the second plurality of multiplexers to the output of the corresponding data register.

13. The system of claim 8 , further comprising:
means for coupling a serial test interface clock signal to a clock input of each data register when the soft-repair mode is selected; and
means for coupling a functional clock signal to the clock input of each data register when the hard-repair mode is selected.

14. A method for repairing a random access memory, comprising:
receiving a mode selection signal indicating a soft-repair mode or a hard-repair mode;
reading soft-repair data from serial test interface logic into a repair data register chain via multiplexing logic in response to the mode selection signal indicating the soft-repair mode, the repair data register chain comprising a plurality of serially interconnected data registers;
reading hard-repair data from fuse-sense logic into the repair data register chain via the multiplexing logic in response to the mode selection signal indicating the hard-repair mode;
providing repair information from outputs of the data registers to a repair information input of the random access memory;
transferring data serially from the serial test interface logic into a control signal register chain comprising a plurality of serially interconnected control signal registers; and
coupling outputs of the control signal registers to control inputs of the multiplexing logic.

15. The method of claim 14 , wherein the serial test interface logic comprises Joint Test Action Group (JTAG) logic.

16. The method of claim 14 , wherein:
reading hard-repair data comprises providing a portion of the hard-repair data to a first input of

Assignees

• Qualcomm Inc

Inventors

• Dai Hong
• Borovietzky Amir
• Jain Arvind
• Bitam Massine
• Krishnappa Madan

Classifications

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G01R31/31926

  Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing · CPC title

• G11C29/789

  using non-volatile cells or latches · CPC title

• G11C29/787

  using a fuse hierarchy · CPC title

• G11C29/76

  using address translation or modifications · CPC title