Pixel circuit, driving method thereof, display substrate and display device

Patent metadata

Field	Value
Publication number	US-12300152-B2
Application number	US-202218022173-A
Country	US
Kind code	B2
Filing date	Jun 17, 2022
Priority date	Jun 17, 2022
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A pixel circuit, a driving method thereof, a display substrate and a display device are disclosed. The pixel circuit includes a driving circuit and a light-emitting element, the driving circuit is configured to provide a driving current and control a conducting duration of a current pathway between the first power supply terminal and the second power supply terminal; the light-emitting element is configured to receive the driving current in the current pathway and emit light; the driving circuit includes a current control sub-circuit and a duration control sub-circuit; the current control sub-circuit is configured to provide a driving current to the first node under the control of the first scanning signal terminal, the first data signal terminal and the first power supply terminal in a display stage and a non-display stage.

First claim

The invention claimed is:

1. A pixel circuit, comprising a driving circuit and a light-emitting element connected in series between a first power supply terminal and a second power supply terminal; the driving circuit is configured to provide a driving current and control a conducting duration of a current pathway between the first power supply terminal and the second power supply terminal; the light-emitting element is configured to receive the driving current in the current pathway and emit light; the driving circuit comprises a current control sub-circuit and a duration control sub-circuit;
the current control sub-circuit, electrically connected to a first scanning signal terminal, a first data signal terminal, a first power supply terminal and a first node, respectively, is configured to provide a driving current to the first node under control of the first scanning signal terminal, the first data signal terminal and the first power supply terminal;
the duration control sub-circuit, electrically connected to a second scanning signal terminal, a third scanning signal terminal, a second data signal terminal, a first control signal terminal, a reset signal terminal, a first initial signal terminal and a second initial signal terminal, the first node and a second node, respectively, is configured to provide a signal of the first node to the second node under control of the second scanning signal terminal, the third scanning signal terminal, the second data signal terminal, the first control signal terminal, the reset signal terminal, the first initial signal terminal and the second initial signal terminal; and
the light-emitting element is electrically connected to the second node and the second power supply terminal, respectively.

2. The pixel circuit according to claim 1 , wherein based on a determination that a signal of the reset signal terminal is an active level signal, signals of the first scanning signal terminal, the second scanning signal terminal and the third scanning signal terminal are inactive level signals;
based on a determination that the signal of the first scanning signal terminal is an active level signal, the signal of the second scanning signal terminal is an active level signal, and the signals of the reset signal terminal and the third scanning signal terminal are inactive level signals;
based on a determination that the signal of the third scanning signal terminal is an active level signal, the signals of the reset signal terminal, the second scanning signal terminal and the third scanning signal terminal are inactive level signals;
a signal of the first control signal terminal is a ramp signal; and
voltage values of signals of the first initial signal terminal and the second initial signal terminal are constant.

3. The pixel circuit according to claim 1 , wherein the current control sub-circuit, electrically connected to a fourth scanning signal terminal, is configured to provide a driving current to the first node under control of the first scanning signal terminal, the fourth scanning signal terminal, the first data signal terminal and the first power supply terminal.

4. The pixel circuit according to claim 3 , wherein based on a determination that a signal of the first scanning signal terminal is an active level signal, a signal of the fourth scanning signal terminal is an active level signal.

5. The pixel circuit according to claim 3 , wherein the current control sub-circuit comprises a first writing sub-circuit, a first storage sub-circuit and a driving sub-circuit;
the first writing sub-circuit, electrically connected to the first scanning signal terminal, the fourth scanning signal terminal, the first data signal terminal and a third node, respectively, is configured to provide a signal of the first data signal terminal to the third node under control of the first scanning signal terminal and the fourth scanning signal terminal;
the first storage sub-circuit, electrically connected to the third node and a third power supply terminal, respectively, is configured to store a voltage difference between signals of the third node and the third power supply terminal, or electrically connected to the first node and the third node, respectively, is configured to store a voltage difference between the signals of the first node and the third node; and
the driving sub-circuit, electrically connected to the first power supply terminal, the first node and the third node, respectively, is configured to provide a driving current to the first node under control of the third node and the first power supply terminal.

6. The pixel circuit according to claim 5 , wherein the first writing sub-circuit comprises a second transistor and a third transistor;
a control electrode of the second transistor is electrically connected to the first scanning signal terminal, a first electrode of the second transistor is electrically connected to the first data signal terminal, and a second electrode of the second transistor is electrically connected to the third node;
a control electrode of the third transistor is electrically connected to the fourth scanning signal terminal, a first electrode of the third transistor is electrically connected to the first data signal terminal, and a second electrode of the third transistor is electrically connected to the third node; and
the second transistor and the third transistor are of different types.

7. The pixel circuit according to claim 3 , wherein the current control sub-circuit comprises a first transistor, a second transistor, a third transistor and a first capacitor, the duration control sub-circuit comprises fifth transistor through ninth transistor and a second capacitor;
a control electrode of the first transistor is electrically connected to a third node, a first electrode of the first transistor is electrically connected to the first power supply terminal, and a second electrode of the first transistor is electrically connected to the first node;
a control electrode of the second transistor is electrically connected to the first scanning signal terminal, a first electrode of the second transistor is electrically connected to the first data signal terminal, and a second electrode of the second transistor is electrically connected to the third node;
a control electrode of the third transistor is electrically connected to a fourth scanning signal terminal, a first electrode of the third transistor is electrically connected to the first data signal terminal, and a second electrode of the third transistor is electrically connected to the third node;
a control electrode of the fifth transistor is electrically connected to a fourth node, a first electrode of the fifth transistor is electrically connected to the first node, and a second electrode of the fifth transistor is electrically connected to the second node;
a control electrode of the sixth transistor is electrically connected to the second scanning signal terminal, a first electrode of the sixth transistor is electrically connected to the second data signal terminal, and a second electrode of the sixth transistor is electrically connected to a fifth node;
a control electrode of the seventh transistor is electrically connected to the third scanning signal terminal, a first electrode of the seventh transistor is electrically connected to the first control signal terminal, and a second electrode of the seventh transistor is electrically connected to the fifth node;
a control electrode of the eighth transistor is electrically connected to the reset signal terminal, a first electrode of the eighth transistor is electrically connected to the first initial signal terminal, and a second electrode of the eighth transistor is electrically connected to the fourth node;
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Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Can
• Cong Ning
• Wang Can
• Niu Jinfei
• Zhang Jingjing
• Xuan Minghua
• Chen Xiaochuan

Classifications

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G3/3208

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title

• G09G3/3225

  using an active matrix · CPC title