Display controller, electronic device, and virtual reality device
US-2017340969-A1 · Nov 30, 2017 · US
US12299189B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12299189-B2 |
| Application number | US-202318497136-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 30, 2023 |
| Priority date | Apr 24, 2017 |
| Publication date | May 13, 2025 |
| Grant date | May 13, 2025 |
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When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
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What is claimed is: 1. An apparatus comprising: a first graphics processing unit comprising: a plurality of texture units, a shared memory coupled to the plurality of texture units, a plurality of register files coupled to the shared memory, a plurality of load/store units coupled to the shared memory, a security engine, a compression circuit to compress and decompress data, and a plurality of graphics processing cores coupled to the shared memory, wherein at least one of the plurality of graphics processing cores is to: receive information to identify a first portion of a frame, apply a first non-normalized shading rate within the first portion of the frame, and apply a second non-normalized shading rate within at least a second portion of the frame, wherein the first non-normalized shading rate is twice the second non-normalized shading rate; and a second graphics processing unit coupled to the first graphics processing unit via an interconnect. 2. The apparatus of claim 1 , further comprising scheduler logic to schedule groups of instructions. 3. The apparatus of claim 1 , further comprising a plurality of arithmetic logic units coupled to the plurality of register files, wherein the plurality of arithmetic logic units are to perform operations on integer data types. 4. The apparatus of claim 1 , further comprising at least one memory unit. 5. The apparatus of claim 4 , wherein the at least one memory unit comprises a load and store unit. 6. The apparatus of claim 1 , further comprising at least one special function unit. 7. The apparatus of claim 1 , wherein the first graphics processing unit comprises a single instruction multiple thread processor. 8. The apparatus of claim 1 , further comprising an interface to communicate with a headset. 9. The apparatus of claim 8 , wherein the interface is to receive motion tracking information from the headset. 10. The apparatus of claim 1 , wherein the at least one of the plurality of graphics processing cores is to receive the information to identify the first portion of the frame based on eye gaze detection. 11. A graphics processing unit comprising: a security engine, a compression circuit to compress and decompress data, a plurality of texture units, a shared memory coupled to the plurality of texture units, a plurality of register files coupled to the shared memory, a plurality of load/store units coupled to the shared memory, and a plurality of graphics processing cores coupled to the plurality of register files, wherein at least one of the plurality of graphics processing cores is to: receive information to identify a portion of a frame as a foveated region, shade the foveated region at a first shading rate, and shade another region of the frame at a second shading rate, wherein the second shading rate is half of the first shading rate and the first shading rate and the second shading rate are non-normalized rates; and an interconnect to couple the graphics processing unit to a central processing unit. 12. The graphics processing unit of claim 11 , further comprising a plurality of arithmetic logic units coupled to the plurality of register files, wherein the plurality of arithmetic logic units are to perform operations on integer data types. 13. The graphics processing unit of claim 11 , further comprising at least one special function unit. 14. The graphics processing unit of claim 11 , wherein the graphics processing unit comprises a single instruction multiple thread processor. 15. The graphics processing unit of claim 11 , further comprising an interface to communicate with a headset. 16. The graphics processing unit of claim 15 , wherein the interface is to receive motion tracking information from the headset. 17. The graphics processing unit of claim 11 , wherein the at least one of the plurality of graphics processing cores is to receive the information to identify the first portion of the frame based on eye gaze detection. 18. A graphics processor comprising: an interconnect to couple to the graphics processor with a processor, a security engine, a compression circuit to compress and decompress data, a plurality of texture units, a shared memory coupled to the plurality of texture units, a plurality of register files coupled to the shared memory, a plurality of load/store units coupled to the shared memory, and a plurality of graphics processing cores coupled to the plurality of register files, wherein at least one of the plurality of graphics processing cores is to: receive information to identify a first portion of a frame based on eye gaze detection, apply a first non-normalized shading rate within the first portion of the frame, apply a second non-normalized shading rate within at least a second portion of the frame, wherein the first non-normalized shading rate is twice the second non-normalized shading rate, transfer the first portion of the frame to a head-mounted display as a first surface, and transfer the second portion of the portion of the frame to the head-mounted display as a second surface. 19. The graphics processor of claim 18 , further comprising an interface to communicate with the head-mounted display. 20. The graphics processor of claim 19 , wherein the at least one of the plurality of graphics processing cores is to receive motion tracking information from the head-mounted display.
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