High-performance, high-capacity memory systems and modules

Patent metadata

Field	Value
Publication number	US-12298926-B2
Application number	US-202318365696-A
Country	US
Kind code	B2
Filing date	Aug 4, 2023
Priority date	Dec 1, 2014
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

First claim

What is claimed is:

1. A memory module comprising:
a first memory component;
a second memory component;
an address-buffer component including:
a primary address interface to receive a primary memory address;
a primary chip-select interface to receive primary chip-select information;
a first secondary chip-select interface connected to the first memory component;
a second secondary chip-select interface connected to the second memory component;
the address-buffer component including:
a mode register to store a mode signal indicative of one of a first operational mode and a second operational mode; and
a multiplexer coupled to the primary address interface and the primary chip-select interface to select one of the primary memory address and the primary chip-select information responsive to the mode signal;
wherein the address-buffer component, in the first operational mode, steers the primary chip-select information to one of the first and second secondary chip-select interfaces and disables the other of the first and second secondary chip-select interfaces responsive to the selected one of the primary memory address and the primary chip-select information.

2. The memory module of claim 1 , wherein the address-buffer component, in the second operational mode, steers the primary chip-select information to both the first secondary chip-select interface and the second secondary chip-select interface.

3. The memory module of claim 2 , wherein the address-buffer component loads the mode register responsive to the primary memory address.

4. The memory module of claim 2 , wherein the address-buffer component further includes a slow-signal interface, and wherein the address-buffer component loads the mode register responsive to control signals on the slow-signal interface.

5. The memory module of claim 1 , wherein the first and second memory components each include row addresses and column addresses, and wherein the primary memory address specifies at least one address of the row addresses and the column addresses.

6. The memory module of claim 1 , wherein the first and second memory components include bank addresses and bank-group addresses, and wherein the primary memory address specifies at least one address of the bank addresses and the bank-group addresses.

7. The memory module of claim 1 , wherein the multiplexer blocks passing of the primary chip-select information responsive to the primary chip-select information.

8. The memory module of claim 1 , further comprising a data-buffer component connected to the first memory component and the second memory component, the data-buffer component to communicate with one of the first memory component and the second memory component responsive to the selected one of the primary memory address and the primary chip-select information.

9. The memory module of claim 1 , wherein the address-buffer component, in the second operational mode, steers the primary chip-select information to one of the first and second secondary chip-select interfaces and disables the other of the first and second secondary chip-select interfaces without regard to either of the primary memory address and the primary chip-select information.

10. An address-buffer component comprising:
a primary address interface to receive a primary memory address;
a primary chip-select interface to receive primary chip-select information;
a first secondary chip-select interface to connect to a first memory component;
a second secondary chip-select interface to connect to a second memory component;
a mode register to store a mode signal indicative of one of a first operational mode and a second operational mode; and
a multiplexer coupled to the primary address interface and the primary chip-select interface to select one of the primary memory address and the primary chip-select information responsive to the mode signal;
the address-buffer component, in the first operational mode, to steer the primary chip-select information to one of the first and second secondary chip-select interfaces and disable the other of the first and second secondary chip-select interfaces responsive to the selected one of the primary memory address and the primary chip-select information.

11. The address-buffer component of claim 10 , the address-buffer component, in the second operational mode, to steer the primary chip-select information to both the first secondary chip-select interface and the second secondary chip-select interface.

12. The address-buffer component of claim 11 , the address-buffer component to load the mode register responsive to the primary memory address.

13. The address-buffer component of claim 11 , the address-buffer component further comprising a slow-signal interface, and the address-buffer component to load the mode register responsive to control signals on the slow-signal interface.

14. The address-buffer component of claim 10 , the first and second memory components to include row addresses and column addresses, and the primary memory address to specify at least one address of the row addresses and the column addresses.

15. The address-buffer component of claim 10 , the first and second memory components to include bank addresses and bank-group addresses, and the primary memory address to specify at least one address of the bank addresses and the bank-group addresses.

16. The address-buffer component of claim 10 , the multiplexer to block passing of the primary chip-select information responsive to the primary chip-select information.

17. The address-buffer component of claim 10 , the address-buffer component, in the second operational mode, to steer the primary chip-select information to one of the first and second secondary chip-select interfaces and disable the other of the first and second secondary chip-select interfaces without regard to either of the primary memory address and the primary chip-select information.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Tsern Ely
• Linstadt John Eric
• Giovannini Thomas J
• Hampel Craig E
• Best Scott C
• Yan John

Classifications

• G06F13/1694

  Configuration of memory controller to different memory types · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F13/1678 Primary

  using bus width · CPC title