Ultrasound imaging with sparse array probes
US-10856846-B2 · Dec 8, 2020 · US
US12295790B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12295790-B2 |
| Application number | US-202318236233-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 21, 2023 |
| Priority date | Mar 22, 2018 |
| Publication date | May 13, 2025 |
| Grant date | May 13, 2025 |
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Described are transducer assemblies and imaging devices comprising: a microelectromechanical systems (MEMS) die including a plurality of piezoelectric elements; a complementary metal-oxide-semiconductor (CMOS) die electrically coupled to the MEMS die by a first plurality of bumps and including at least one circuit for controlling the plurality of piezoelectric elements; and a package secured to the CMOS die by an adhesive layer and electrically connected to the CMOS die.
Opening claim text (preview).
What is claimed is: 1. A transducer assembly, comprising: a complementary metal-oxide-semiconductor (CMOS) die; a microelectromechanical systems (MEMS) die electrically coupled to a first side of the CMOS die by a first plurality of bumps and comprising at least one piezoelectric element for imaging a target; and a package electrically connected to a second side of the CMOS die by a second plurality of bumps. 2. The transducer assembly of claim 1 , wherein the MEMS die includes a plurality of piezoelectric elements. 3. The transducer assembly of claim 2 , wherein each of the plurality of piezoelectric elements includes a substrate and a cavity formed in the substrate to define a membrane. 4. The transducer assembly of claim 2 , wherein each of the plurality of piezoelectric elements includes a substrate and a membrane layer formed by depositing SiO 2 on the substrate. 5. The transducer assembly of claim 2 , wherein two or more piezoelectric elements may be connected to form a larger pixel element. 6. The transducer assembly of claim 1 , wherein the package is further secured to the CMOS die by an adhesive layer. 7. The transducer assembly of claim 1 , wherein the package is additionally electrically connected to the CMOS die by one or more wires. 8. The transducer assembly of claim 1 , wherein the package is additionally electrically connected to the CMOS die by through-vias. 9. The transducer assembly of claim 1 , wherein the transducer assembly is contained within a housing and further comprises a heat dissipation mechanism. 10. The transducer assembly of claim 1 , wherein space between the MEMS die and CMOS die is filled with an underfill material. 11. The transducer assembly of claim 10 , wherein the underfill material mechanically secures the MEMS die to the CMOS die. 12. The transducer assembly of claim 10 , wherein the underfill material has acoustic damping properties to absorb pressure waves that pass through the underfill material. 13. The transducer assembly of claim 1 , further comprising a seal ring disposed around a perimeter of the MEMS die with space enclosed by the seal ring kept in vacuum or in low pressure. 14. The transducer assembly of claim 1 , further comprising a cover layer disposed around the MEMS die, wherein the cover layer functions as an impedance matching layer between the MEMS die and a human body. 15. An imaging device comprising: an electrical stack having a microelectromechanical systems (MEMS) die, a plurality of piezoelectric elements coupled to the MEMS die, and a complementary metal-oxide-semiconductor (CMOS) die electrically coupled to the MEMS die; and a package that receives and processes electrical signals from the electrical stack, wherein pillars connect both the MEMS die to the CMOS die and the CMOS die to the package. 16. The device of claim 15 , wherein each of the plurality of piezoelectric elements forms a piezoelectric micromachined ultrasonic transducer (pMUT) with a bottom electrode, a piezoelectric layer, and a top electrode. 17. The device of claim 16 , further comprising a plurality of integrated circuits for controlling the pMUTs, the plurality of integrated circuits being formed in the CMOS die. 18. The device of claim 15 , further comprising a display for displaying an image based on signals processed by the imaging device. 19. The device of claim 15 , wherein the CMOS die and the package are further connected by through-vias (TVS). 20. The device of claim 15 , wherein the CMOS die is located between the MEMS die and the package.
characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title
the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title
batch processes · CPC title
Die-attach connectors and bond wires · CPC title
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
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