Display device

US12295220B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12295220-B2
Application numberUS-202117154922-A
CountryUS
Kind codeB2
Filing dateJan 21, 2021
Priority dateSep 9, 2020
Publication dateMay 6, 2025
Grant dateMay 6, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display device includes a substrate, a transistor, an interlayer insulating layer, a first conductive line, a pixel electrode, a passivation layer, a common electrode, and a light emitting element layer. The transistor overlaps the substrate. The interlayer insulating layer overlaps the transistor and includes a first groove. The first conductive line is electrically connected to the transistor and is at least partially disposed inside the first groove. The pixel electrode is electrically connected to the transistor and overlaps the first conductive line. The passivation layer is disposed between the pixel electrode and the first conductive line and directly contacts at least one of the pixel electrode and the first conductive line. The common electrode overlaps the pixel electrode. The light emitting element layer is disposed between the common electrode and the pixel electrode.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device comprising: a substrate; a transistor overlapping the substrate and comprising a semiconductor layer, a source electrode or a drain electrode, wherein the source electrode or the drain electrode directly contacts the semiconductor layer; an interlayer insulating layer overlapping the transistor and including a first groove and a second groove; a first conductive line electrically connected to the transistor, disposed on the interlayer insulating layer and at least partially disposed inside the first groove, the interlayer insulating layer overlapping the source electrode or the drain electrode of the transistor; a first data line electrically connected to the transistor, disposed on the interlayer insulating layer and at least partially disposed inside the second groove, the interlayer insulating layer overlapping the source electrode or the drain electrode of the transistor; a pixel electrode electrically connected to the first conductive line through the transistor and overlapping the first conductive line; a passivation layer disposed between the pixel electrode and the first conductive line and directly contacting at least one of the pixel electrode and the first conductive line; a common electrode overlapping the pixel electrode; and a light emitting element layer disposed between the common electrode and the pixel electrode, wherein the interlayer insulating layer includes a first portion overlapping the first conductive line and a second portion excluding the first portion, and a thickness of the first portion is less than a thickness of the second portion, and wherein the passivation layer is in a direct contact with a part of the first groove and the second groove. 2. The display device of claim 1 , wherein the first conducive line is a driving voltage line. 3. The display device of claim 2 , wherein a depth of the first groove is equal to a thickness of the driving voltage line in a thickness direction of the driving voltage line, and a depth of the second groove is equal to a thickness of the first data line in a thickness direction of the first data line. 4. The display device of claim 2 , wherein a width of the first groove is greater than or equal to a width of the driving voltage line in a cross section of the display device, and a width of the second groove is greater than or equal to a width of the first data line in the cross section of the display device. 5. The display device of claim 2 , further comprising a second data line, wherein the second data line is spaced from the first data line and is at least partially disposed inside the second groove. 6. The display device of claim 2 , wherein exactly one data line is disposed in the second groove. 7. The display device of claim 1 , wherein the interlayer insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer is disposed between the second insulating layer and the substrate, and the first conductive line directly contacts a face of the first insulating layer and is disposed between two sections of the second insulating layer. 8. The display device of claim 7 , wherein the face of the first insulating layer directly contacts the two sections of the second insulating layer. 9. The display device of claim 1 , further comprising a driving voltage line, wherein the driving voltage line is spaced from the first conductive line and is at least partially disposed inside the first groove. 10. The display device of claim 1 , further comprising: an encapsulation layer overlapping the common electrode; a light blocking layer overlapping the encapsulation layer; and a color filter overlapping the pixel electrode and directly contacting the light blocking layer. 11. The display device of claim 1 , wherein the semiconductor layer of the transistor is composed of at least one of an oxide semiconductor and a polycrystalline semiconductor.

Assignees

Inventors

Classifications

  • comprising light absorbing layers, e.g. black layers · CPC title

  • multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers · CPC title

  • Shielding, e.g. light-blocking means over the TFTs · CPC title

  • H10K59/122Primary

    Pixel-defining structures or layers, e.g. banks · CPC title

  • comprising colour filters or colour changing media [CCM] · CPC title

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Frequently asked questions

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What does patent US12295220B2 cover?
A display device includes a substrate, a transistor, an interlayer insulating layer, a first conductive line, a pixel electrode, a passivation layer, a common electrode, and a light emitting element layer. The transistor overlaps the substrate. The interlayer insulating layer overlaps the transistor and includes a first groove. The first conductive line is electrically connected to the transist…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/122. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 06 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).