Method for manufacturing metal gate of PMOS

Patent metadata

Field	Value
Publication number	US-12295153-B2
Application number	US-202217945356-A
Country	US
Kind code	B2
Filing date	Sep 15, 2022
Priority date	Oct 29, 2021
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

The present application discloses a method for manufacturing a metal gate of a PMOS, comprising: step 1, forming a P-type work function metal layer; step 2, depositing an N-type work function metal layer by means of a PVD process, wherein over a bottom surface of a gate trench, the N-type work function metal layer has a hill profile; step 3, forming a first top barrier metal sublayer by means of a conformal growth process, wherein the first top barrier metal sublayer completely fills a sharp corner area of the N-type work function metal layer at a corner of the gate trench; step 4, growing a second top barrier metal sublayer by means of a PVD bombardment process; step 5, forming a third top barrier metal sublayer and a fourth top barrier metal sublayer; and step 6, forming a metal conductive material layer.

First claim

What is claimed is:

1. A method for manufacturing a metal gate of a PMOS, comprising steps of:
step 1, forming a P-type work function metal layer, the P-type work function metal layer being formed on a bottom surface and a side surface of a gate trench;
step 2, depositing an N-type work function metal layer by means of a physical vapor deposition (PVD) process, the N-type work function metal layer being formed on a surface of the P-type work function metal layer, wherein over the bottom surface of the gate trench, the N-type work function metal layer has a hill profile composed of a thicker portion located at a middle area of the gate trench and a thinner portion located at the side surface of the gate trench, and the hill profile enables the N-type work function metal layer to have a sharp corner less than 90 degrees at a corner of the gate trench;
step 3, forming a first top barrier metal sublayer on a surface of the N-type work function metal layer by means of a conformal growth process, wherein, due to properties of conformal growth, the first top barrier metal sublayer completely fills a sharp corner area of the N-type work function metal layer at the corner of the gate trench;
step 4, growing a second top barrier metal sublayer by means of a PVD bombardment process, wherein the PVD bombardment process increases a vertical bias while growing the second top barrier metal sublayer, so as to achieve vertical bombardment on the first top barrier metal sublayer and the second top barrier metal sublayer, increasing atomic density of the first top barrier metal sublayer and causing sputtering of materials of the first top barrier metal sublayer and the second top barrier metal sublayer that are deposited at the middle area on the bottom surface of the gate trench to the corner of the gate trench, thereby increasing a thickness of a stack layer of the first top barrier metal sublayer and the second top barrier metal sublayer at the corner of the gate trench and making an opening profile of the second top barrier metal sublayer in the gate trench be U-shaped;
step 5, sequentially forming a third top barrier metal sublayer and a fourth top barrier metal sublayer by means of a PVD process, wherein the first top barrier metal sublayer, the second top barrier metal sublayer, the third top barrier metal sublayer, and the fourth top barrier metal sublayer are stacked to form a top barrier metal layer; and
step 6, forming a metal conductive material layer to completely fill the gate trench.

2. The method for manufacturing the metal gate of the PMOS according to claim 1 , wherein in step 2, a material of the N-type work function metal layer comprises TiAl.

3. The method for manufacturing the metal gate of the PMOS according to claim 1 , wherein in step 3, a material of the first top barrier metal sublayer comprises TiN or TaN.

4. The method for manufacturing the metal gate of the PMOS according to claim 3 , wherein in step 3, the conformal growth process of the first top barrier metal sublayer is an atomic layer deposition (ALD) process.

5. The method for manufacturing the metal gate of the PMOS according to claim 3 , wherein in step 4, a material of the second top barrier metal sublayer comprises Ti.

6. The method for manufacturing the metal gate of the PMOS according to claim 5 , wherein in step 4, the vertical bias of the PVD bombardment process is 500 w-1200 w.

7. The method for manufacturing the metal gate of the PMOS according to claim 5 , wherein in step 5, a material of the third top barrier metal sublayer comprises TiN.

8. The method for manufacturing the metal gate of the PMOS according to claim 7 , wherein in step 5, a material of the fourth top barrier metal sublayer comprises Ti.

9. The method for manufacturing the metal gate of the PMOS according to claim 1 , wherein a material of the metal conductive material layer comprises Al.

10. The method for manufacturing the metal gate of the PMOS according to claim 4 , wherein a thickness of the first top barrier metal sublayer is 10 Å-30 Å.

11. The method for manufacturing the metal gate of the PMOS according to claim 5 , wherein a thickness of the second top barrier metal sublayer is 10 Å-30 Å.

12. The method for manufacturing the metal gate of the PMOS according to claim 8 , wherein a thickness of the stack layer of the third top barrier metal sublayer and the fourth top barrier metal sublayer is 90 Å-130 Å.

13. The method for manufacturing the metal gate of the PMOS according to claim 1 , wherein in step 1, a material of the P-type work function metal layer comprises TiN.

14. The method for manufacturing the metal gate of the PMOS according to claim 1 , wherein in step 1, the gate trench is formed by removing a dummy polysilicon gate.

15. The method for manufacturing the metal gate of the PMOS according to claim 14 , wherein a gate dielectric layer and a bottom barrier metal layer are formed between a bottom of the P-type work function metal layer and a surface of a semiconductor substrate.

16. The method for manufacturing the metal gate of the PMOS according to claim 15 , wherein the gate dielectric layer comprises an interface layer and a high dielectric constant layer stacked in sequence.

Assignees

• Shanghai Huali Integrated Circuit Corp

Inventors

• Zeng Zhaoqin
• Zhang Yu
• Fang Jingxun
• Bao Yu
• Xu Jianhua

Classifications

• H10D64/0133

  at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall · CPC title

• H10D64/01324 Primary

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• C23C28/34

  including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates · CPC title

• C23C28/32

  including at least one pure metallic layer · CPC title