Adaptive correlated multiple sampling

Patent metadata

Field	Value
Publication number	US-12294804-B2
Application number	US-202318322431-A
Country	US
Kind code	B2
Filing date	May 23, 2023
Priority date	May 23, 2023
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.

First claim

What is claimed is:

1. An arithmetic logic circuit (ALU), comprising:
a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs of the GC generator in response to a comparator output;
a signal latch stage coupled to latch outputs of the front end latch stage in response to a signal latch enable signal;
a GC to binary stage coupled to generate a binary representation of the GC outputs latched in the signal latch stage;
an adder stage including first inputs and second inputs, wherein the first inputs of the adder stage are coupled to receive outputs of the GC to binary stage, wherein outputs of the adder stage are generated in response to the first inputs and the second inputs of the adder stage;
a pre-latch stage coupled to latch outputs of the adder stage in response to a pre-latch enable signal; and
a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal, wherein the second inputs of the adder stage are coupled to receive outputs of the feedback latch stage,
wherein the feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal,
wherein the ALU is configured to perform CMS calculations in response to the CMS feedback enable signal, and
wherein the ALU is configured to perform non-CMS calculations in response to the non-CMS feedback enable signal.

2. The ALU of claim 1 , wherein the outputs of the feedback latch stage include first outputs and second outputs, wherein the first outputs of the feedback latch stage are the latched outputs of the pre-latch stage, wherein the second outputs of the feedback latch stage are inverted latched outputs of the pre-latch stage, and wherein the ALU further comprises:
a first multiplexer coupled between the feedback latch stage and the adder stage, wherein the first multiplexer is configured to couple either the first outputs or the second outputs of the feedback latch stage to the second inputs of the adder stage in response to an adder operation signal.

3. The ALU of claim 1 , further comprising a second multiplexer coupled to the feedback latch stage, wherein the second multiplexer is coupled to receive the CMS feedback enable signal and a non-CMS feedback enable signal, wherein the second multiplexer is configured to select one of the CMS feedback enable signal and the non-CMS feedback enable signal in response to an image signal size signal to generate the feedback latch enable signal.

4. The ALU of claim 3 , further comprising a select CMS latch coupled to latch the comparator output in response to a set CMS signal, wherein the select CMS latch is configured to generate the image signal size signal.

5. The ALU of claim 4 , further comprising an image signal size latch coupled to latch the outputs of the select CMS latch in response to a data latch enable signal.

6. The ALU of claim 5 , further comprising a data latch stage coupled to latch outputs of the pre-latch stage in response to the data latch enable signal.

7. The ALU of claim 1 , further comprising an error correction multiplexer coupled between the GC to binary stage and the adder stage, wherein the error correction multiplexer is coupled to receive the outputs of the GC to binary stage and an error correction bitline signal, wherein the multiplexer stage is coupled to generate error correction multiplexer outputs in response to an error correction select signal, and wherein the first inputs of the adder stage are coupled to receive the multiplexer stage outputs.

8. The ALU of claim 1 , wherein the comparator output is generated in response to a comparison between a bitline signal and a ramp signal, wherein the ramp signal includes a plurality of image signal ramp events, wherein a transition in the set CMS signal is configured to occur when one or more of the plurality of image signal ramp events occur in the ramp signal.

9. The ALU of claim 8 , wherein a last one of the image signal ramp events is longer than remaining ones of the image signal ramp events.

10. The ALU of claim 8 , wherein a first one of the image signal ramps is longer than remaining ones of the image signal ramp signal events.

11. The ALU of claim 1 , further comprising a comparator latch coupled to latch the comparator output in response to a comparator latch enable signal, wherein the front end latch stage coupled to latch GC outputs of the GC generator in response to an output of the comparator latch.

12. The ALU of claim 11 , wherein the comparator output is generated in response to a comparison between a bitline signal and a ramp signal, wherein the ramp signal includes a plurality of reset signal ramp events and a plurality of image signal ramp events, wherein a first one of the image signal ramp events is longer than remaining ones of the image signal ramp events, wherein the comparator latch enable signal is configured to be zero-pulsed during the remaining ones of the image signal ramp events, wherein the comparator latch enable signal is configured to remain high during the reset signal ramp events, and wherein a pixel reset clamp is configured to clamp a pixel output during the reset signal ramp events and enable the ALU to perform analog black sun compensation.

13. The ALU of claim 11 , wherein the comparator output is generated in response to a comparison between a bitline signal and a ramp signal, wherein the ramp signal includes a plurality of reset signal ramp events and a plurality of image signal ramp events, wherein a first one of the image signal ramp events is longer than remaining ones of the image signal ramp events, wherein the comparator latch enable signal is configured to be zero-pulsed during the remaining ones of the image signal ramp events, wherein the comparator latch enable signal is configured to be zero-pulsed during each of the reset signal ramp events, and wherein a GC generator reset signal is configured to be pulsed while the comparator latch enable signal is zero-pulsed during each of the reset signal ramp events and enable the ALU to perform digital black sun compensation.

14. The ALU of claim 1 , wherein the ALU is one of a plurality of ALUs coupled to a pixel array of an imaging system, wherein the plurality of ALUs are configured to determine a difference between an accumulated sum of one or more signal level samples and an accumulated sum of one or more black level samples from each of a plurality of pixel circuits of the pixel array.

15. An imaging system, comprising:
a plurality of comparators coupled to receive a global ramp signal;
a gray code (GC) generator; and
a plurality of arithmetic logic units (ALUs) coupled to receive comparator outputs from corresponding ones of the comparators and to receive GC outputs generated by the GC generator, wherein each one of the ALUs comprises:
a front end latch stage coupled to the GC generator to latch the GC outputs of the GC generator in response to a corresponding one of the comparator outputs;
a signal latch stage coupled to latch outputs of the front end latch stage in response to a signal latch enable signal;
a GC to binary stage coupled to generate a binary representation of the GC outputs latched in the signal latch stage;
an adder stage including first inputs and second inputs, wherein the first inputs of the adder stage are coupled to receive outputs of the GC to binary stage, wherein outputs of the adder stage are generated in response to the first inputs and the second inputs of the adder stage;
a pre-latch stage coupled to latch outputs of the adder stage in response to a pre-latch e

Assignees

• Omnivision Tech Inc

Inventors

• Guo Jiayu
• Ebihara Hiroaki
• Zuo Liang
• Fan Lihang
• Sakurai Satoshi

Classifications

• H04N25/616

  involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/78 Primary

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• G06F7/57

  Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} · CPC title

• H03K5/22

  Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral (indicating phase difference of two cyclic pulse trains G01R25/00) · CPC title