Image sensor for performing an analog binning operation

Patent metadata

Field	Value
Publication number	US-12294803-B2
Application number	US-202318296998-A
Country	US
Kind code	B2
Filing date	Apr 7, 2023
Priority date	Sep 6, 2022
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

Disclosed is an image sensor including first to fourth, fifth to eighth, ninth to 12 th and 13 th to 16 th unit pixel circuits, a first readout line connected to the first and ninth unit pixel circuits, a second readout line connected to the fifth and 13 th unit pixel circuits, a third readout line connected to the second and 10 th unit pixel circuits, a fourth readout line connected to the sixth and 14 th unit pixel circuits, a fifth readout line connected to the third and 11 th unit pixel circuits, a sixth readout line connected to the seventh and 15 th unit pixel circuits, a seventh readout line connected to the fourth and 12 th unit pixel circuits, an eighth readout line connected to the eighth and 16 th unit pixel circuits, first to fourth readout circuits, and a path selector connecting the unit pixel circuits to the readout circuits via the readout lines.

First claim

What is claimed is:

1. An image sensor comprising:
a first pixel group including first to fourth unit pixel circuits arranged in at least one row;
a second pixel group including fifth to eighth unit pixel circuits arranged in at least one other row;
a third pixel group including ninth to 12 th unit pixel circuits arranged in at least one other row;
a fourth pixel group including 13 th to 16 th unit pixel circuits arranged in at least one other row;
a first readout line disposed in a first column and connected to the first unit pixel circuit and the ninth unit pixel circuit;
a second readout line disposed in a second column and connected to the fifth unit pixel circuit and the 13 th unit pixel circuit;
a third readout line disposed in a third column and connected to the second unit pixel circuit and the 10 th unit pixel circuit;
a fourth readout line disposed in a fourth column and connected to the sixth unit pixel circuit and the 14 th unit pixel circuit;
a fifth readout line disposed in a fifth column and connected to the third unit pixel circuit and the 11 th unit pixel circuit;
a sixth readout line disposed in a sixth column and connected to the seventh unit pixel circuit and the 15 th unit pixel circuit;
a seventh readout line disposed in a seventh column and connected to the fourth unit pixel circuit and the 12 th unit pixel circuit;
an eighth readout line disposed in an eighth column and connected to the eighth unit pixel circuit and the 16 th unit pixel circuit;
first to fourth readout circuits; and
a path selector suitable for, during a single row time in a binning mode, connecting the first to 16 th unit pixel circuits to the first to fourth readout circuits via the first to eighth readout lines and connecting at least two readout lines of the first to eighth readout lines to one readout circuit of the first to fourth readout circuits.

2. The image sensor of claim 1 , wherein the path selector is further suitable for connecting one of the first to fourth pixel groups to the first to fourth readout circuits via a half of the first to eighth readout lines during the single row time in a normal mode.

3. The image sensor of claim 1 ,
further comprising first to fourth bias circuits,
wherein the path selector is further suitable for connecting the first to eighth readout lines to the first to fourth bias circuits during the single row time in the binning mode.

4. The image sensor of claim 3 , wherein the path selector includes:
a first path selection circuit suitable for selectively connecting the first to eighth readout lines to the first to fourth bias circuits on the basis of a plurality of first control signals; and
a second path selection circuit suitable for selectively connecting the first to eighth readout lines to the first to fourth readout circuits on the basis of a plurality of second control signals.

5. The image sensor of claim 1 ,
further comprising first to eighth bias circuits,
wherein the path selector is further suitable for connecting the first to eighth readout lines to the first to eighth bias circuits, respectively, during the single row time in the binning mode.

6. The image sensor of claim 5 , wherein the path selector includes:
a first path selection circuit suitable for selectively connecting the first to eighth readout lines to the first to fourth bias circuits on the basis of a plurality of first control signals; and
a second path selection circuit suitable for selectively connecting the first to eighth readout lines to the first to fourth readout circuits on the basis of a plurality of second control signals.

7. The image sensor of claim 1 , the at least two readout lines are connected to an input terminal of the one readout circuit.

8. The image sensor of claim 1 , wherein the path selector performs an analog binning operation on first to 16th unit pixel signals generated from the first to 16th unit pixel circuits to output first to fourth selection pixel signals to first to fourth readout circuits.

9. An image sensor comprising:
a pixel array of N×M unit pixel circuits, where N≥2 and M≥N;
K*N readout lines connected to the N×M unit pixel circuits of the pixel array, where K≥2;
a signal converter including N readout circuits; and
a path selector suitable for, during a single row time in a binning mode, connecting at least two readout lines of the K*N readout lines to one readout circuit of N readout circuits when connecting the N×M unit pixel circuits of the pixel array to the N readout circuits via the K*N readout lines and connecting the N×M unit pixel circuits of the pixel array to the N readout circuits by connecting at least four unit pixel circuits arranged in at least two rows among the N×M unit pixel circuits of the pixel array to one of the N readout circuits.

10. The image sensor of claim 9 , wherein the path selector is further suitable for connecting N×1 unit pixel circuits among the N×M unit pixel circuits of the pixel array to the N readout circuits, respectively, via some or all of the K*N readout lines during the single row time in a normal mode.

11. The image sensor of claim 9 ,
further comprising a bias generator including N bias circuits,
wherein the path selector is further suitable for connecting the N×M unit pixel circuits of the pixel array to the N bias circuits via the K*N readout lines during the single row time in the binning mode.

12. The image sensor of claim 11 , wherein the path selector includes:
a first path selection circuit suitable for selectively connecting the K*N readout lines to the N bias circuits on the basis of a plurality of first control signals; and
a second path selection circuit suitable for selectively connecting the K*N readout lines to the N readout circuits on the basis of a plurality of second control signals.

13. The image sensor of claim 9 ,
further comprising a bias generator including K*N bias circuits,
wherein the path selector is further suitable for connecting the N×M unit pixel circuits of the pixel array to the K*N bias circuits via the K*N readout lines during the single row time in the binning mode.

14. The image sensor of claim 13 , wherein the path selector includes:
a first path selection circuit suitable for selectively connecting the K*N readout lines to the K*N bias circuits on the basis of a plurality of first control signals; and
a second path selection circuit suitable for selectively connecting the K*N readout lines to the N readout circuits on the basis of a plurality of second control signals.

Assignees

• Sk Hynix Inc

Inventors

• Kim Dong Ju

Classifications

• H10F39/803 Primary

  Pixels having integrated switching, control, storage or amplification elements · CPC title

• H04N25/46 Primary

  by combining or binning pixels · CPC title

• H04N25/78 Primary

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N25/767

  Horizontal readout lines, multiplexers or registers · CPC title