Adaptive digital pre-distortion

Patent metadata

Field	Value
Publication number	US-12294396-B2
Application number	US-202217812611-A
Country	US
Kind code	B2
Filing date	Jul 14, 2022
Priority date	Jul 14, 2022
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, an apparatus may receive an indication of a selected digital pre-distortion (DPD) kernel from multiple DPD kernels. The apparatus may store multiple envelope values associated of with samples of an in-phase/quadrature (I/Q) signal and select a subset of envelope values based at least in part on the selected DPD kernel. The apparatus may generate, using the subset of envelope values and a look-up-table (LUT) component, an envelope computation value. The apparatus may store multiple computational values associated with the samples and select, based at least in part on the selected DPD kernel, at least one subset of computational values. The apparatus may generate an output sample that includes DPD based at least in part on combining the envelope computation value with the at least one subset of computational values. Numerous other aspects are described.

First claim

What is claimed is:

1. An apparatus comprising:
a first input mechanism configured to receive an indication of a selected digital pre-distortion (DPD) kernel from a plurality of DPD kernels;
an envelope delay line component comprising an envelope storage component configured to store an input envelope value as one of a plurality of envelope values associated with a plurality of samples that are sampled over a time duration;
an envelope selection component configured to select a subset of envelope values from the plurality of envelope values based at least in part on the selected DPD kernel;
at least one look-up-table (LUT) component coupled to the envelope selection component configured to:
receive the subset of envelope values and
output an envelope computation value that is based at least in part on the subset of envelope values and the selected DPD kernel;

a computation delay line component comprising a computation storage component configured to store at least:
a first plurality of computational values that are based at least in part on a first computation applied to each sample of the plurality of samples;
a second plurality of computational values that are based at least in part on a second computation applied to each sample of the plurality of samples; and
the plurality of samples that span the time duration;

at least one computation selection component coupled to the computation delay line component and configured to select, based at least in part on the selected DPD kernel, at least one subset of computational values stored by the computation storage component; and
at least one combiner component coupled to the at least one computation selection component and the at least one LUT component, the at least one combiner component configured to generate an output sample based at least in part on combining the envelope computation value with the at least one subset of computational values.

2. The apparatus of claim 1 , wherein the at least one LUT component comprises multiple LUT components, and wherein the apparatus further comprises:
at least one LUT selection component that couples the multiple LUT components to the at least one combiner component, the at least one LUT selection component configured to:
select a subset of LUT outputs from the multiple LUT components based at least in part on the selected DPD kernel; and
input the subset of LUT outputs to the at least one combiner component.

3. The apparatus of claim 1 , wherein the at least one combiner component comprises a first set of combiner components and a second combiner component, and wherein the apparatus further comprises:
at least one value selection component that couples the first set of combiner components to the second combiner component, the at least one value selection component configured to:
select a subset of combined values output from the first set of combiner components based at least in part on the selected DPD kernel; and
input the subset of combined values to the second combiner component.

4. The apparatus of claim 1 , wherein the envelope selection component comprises a delay line-multiplexer selection component.

5. The apparatus of claim 4 , wherein the delay line-multiplexer selection component comprises:
a delay line component;
a first multiplexer component coupled to at least one input of the delay line component; and
a second multiplexer component coupled to at least one output of the delay line component.

6. The apparatus of claim 1 , wherein the at least one LUT component stores at least one envelope computation value that is based at least in part on a piece-wise linear envelope function associated with a distortion model.

7. The apparatus of claim 1 , wherein the at least one LUT component stores at least one approximate envelope power summation value that is based at least in part on an approximation of a signal envelope summation function.

8. The apparatus of claim 1 , wherein the plurality of DPD kernels comprises at least one of:
a dynamic deviation reduction (DDR) DPD kernel,
a generalized DDR (GDDR) DPD kernel,
a generalized memory polynomial (GMP) DPD kernel, or
a decomposed vector rotation (DVR) DPD kernel.

9. The apparatus of claim 1 , wherein the envelope computation value comprises an envelope power summation value associated with a Volterra-based DPD kernel.

10. The apparatus of claim 1 , wherein the envelope computation value is based at least in part on a piece-wise linear envelope function associated with a decomposed vector rotation (DVR) DPD kernel.

11. The apparatus of claim 1 , wherein the envelope selection component comprises a selection circuit configured to select the subset of envelope values based at least in part on at least one of:
a timing advance relative to a computation time reference, or
a timing delay relative to the computation time reference.

12. The apparatus of claim 1 , wherein the computation storage component comprises:
a first computation delay line to store the first plurality of computational values; and
a second computation delay line to store the second plurality of computational values.

13. The apparatus of claim 1 , wherein the computation selection component includes a selection logic circuit configured to select one or more samples from the plurality of samples, and
wherein the at least one combiner component is configured to generate the output sample based at least in part on the one or more samples.

14. The apparatus of claim 1 , wherein the at least one combiner component includes a logic circuit configured to combine the envelope computation value with the at least one subset of computational values based at least in part on a summation computation.

15. A method performed by an apparatus, the method comprising:
receiving an indication of a selected digital pre-distortion (DPD) kernel from a plurality of DPD kernels;
storing, based at least in part on an envelope delay line component, an envelope value associated with a sample of an in-phase/quadrature (I/Q) signal, the storing comprising storing the envelope value as one of a plurality of envelope values that span a time duration, the plurality of envelope values based at least in part on a plurality of samples associated with the I/Q signal;
storing, based at least in part on a computation storage component, at least:
a first computational value as one of a first plurality of computational values, the first plurality of computational values being based at least in part on the plurality of samples, the first computational value being based at least in part on a first computation applied to the sample;
a second computational value as one of a second plurality of computational values, the second plurality of computational values being based at least in part on the plurality of samples, the second computational value being based at least in part on a second computation applied to the sample; and
the plurality of samples;

selecting a subset of envelope values from the plurality of envelope values based at least in part on the selected DPD kernel;
generating, based at least in part on the subset of envelope values, at least one look-up-table (LUT) component, and the selected DPD kernel, an envelope computation value;
selecting, based at least in part on the selected DPD kernel, at least one subset of computational values stored by the computation storage component; and
generating an output sample that includes digital pre-distortion based at least in part on combining the envelope computation value with the at least one subset of computational values.

Assignees

• Qualcomm Inc

Inventors

• Levitan Evgeny
• Hemo Evyatar
• Bino Moshe
• Sagi Ariel
• Antsiferov Ilia
• Sanderovich Amichai

Classifications

• H04L25/03853

  Shaping by digital methods other than look up tables or up/down converters · CPC title

• H04B2001/0425

  with linearisation using predistortion · CPC title

• H03F1/3247

  using feedback acting on predistortion circuits (H03F1/3264 takes precedence) · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F3/245

  with semiconductor devices only · CPC title