Offset calibration method and circuit applied to comparator array

Patent metadata

Field	Value
Publication number	US-12294378-B1
Application number	US-202519011735-A
Country	US
Kind code	B1
Filing date	Jan 7, 2025
Priority date	Mar 20, 2024
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

Disclosed are an offset calibration method and circuit applied to a comparator array. The offset calibration circuit includes a global calibration voltage generation module, integrators, comparators, a global logic control circuit, and local logic control circuits; an entire comparator array shares the single global calibration voltage generation module, and each of the comparators only needs to introduce an integrator circuit, such that a large calibration range and a small calibration step are achieved, a long calibration cycle and a large circuit area are required, and the requirements for a low area are satisfied. The offset calibration method provided by the present disclosure is similar to a binary search algorithm, which is adopted to search for the offset voltage, the calibration step of
1 2 N ⁢ Vref
can be realized by only N cycles, and short calibration time is thus realized.

First claim

What is claimed is:

1. An offset calibration circuit applied to a comparator array, comprising a global calibration voltage generation module, integrators, comparators, a global logic control circuit, and local logic control circuits, wherein an output terminal of the global logic control circuit is connected to a control terminal of the global calibration voltage generation module, and is configured to generate a control signal required by the global calibration voltage generation module; an output terminal of the global calibration voltage generation module is connected to input terminals of the integrators and is configured to generate a voltage required for calibrating the entire comparator array; one comparator is arranged for every two integrators, output terminals of the two integrators are connected to calibration terminals of one comparator, respectively, and the integrators are configured to integrate the voltage generated by the global calibration voltage generation module in a calibration phase, and to maintain the calibration voltage after integration in a normal working phase of the comparator; and input terminals of the local logic control circuits are connected to output terminals of the comparators, output terminals of the local logic control circuits are connected to control terminals of the integrators and are configured to generate control signals required by the integrators.

2. The offset calibration circuit applied to a comparator array according to claim 1 , wherein the one comparator has two calibration terminals Vcal_P and Vcal_N, and the calibration terminals Vcal_P and Vcal_N are gates of calibration pair transistors connected in parallel with input pair transistors of the comparator or are substrates of the input pair transistors of the comparator.

3. The offset calibration circuit applied to a comparator array according to claim 1 , wherein when the calibration is started, the global logic control circuit generates a control signal to control the global calibration voltage generation module to generate a global calibration voltage Vgcal with sequentially magnitudes of

Vref
,

1
2

⁢
Vref

,

1
4

⁢
Vref
⁢

……
⁢

1

2
N

⁢
Vref

after the comparator makes comparison each time.

4. The offset calibration circuit applied to a comparator array according to claim 1 , wherein the global calibration voltage generation module is composed of a capacitor array, a reset switch, a switch array and a buffer; the capacitor array is connected in parallel, a lower plate of each of the capacitors is connected to one switch, an upper plate of each of the capacitors is connected to a positive terminal of the buffer, and a negative terminal of the buffer is connected to the global calibration voltage Vgcal; the switch array is connected to the global logic control circuit, the global logic control circuit controls each of the switches to be connected to a reference voltage or a ground, the reset switch is connected in parallel to the capacitor array; and when the reset switch is closed, upper plates of all of the capacitors are connected to the reference voltage for resetting the capacitor array.

5. The offset calibration circuit applied to a comparator array according to claim 1 , wherein the integrators consist of switches S int1 -S int5 , capacitors C int1 -C int3 , a 2× gain amplifier, and one selector, the capacitors C int1 -C int3 have equal capacitance, and the selector is controlled by a control signal CRE:
when the CRE is at a high level, an upper plate of the capacitor C int2 is connected between the switch S int2 and the switch S int3 , while the capacitor C int3 is connected to an output terminal of one integrator;
when the CRE is at a low level, an upper plate of the capacitor C int3 is connected between the switch S int2 and the switch S int3 , while the capacitor C int2 is connected to an output terminal of one integrator; and
the global calibration voltage Vgcal is connected to an upper plate of the capacitor Cinti through the switch S int1 , the upper plate of the capacitor C int1 is connected to the upper plate of the capacitor C int2 through the switch S int2 , the upper plate of the capacitor C int2 is connected to an input terminal of the 2× gain amplifier through the switch S int3 , an output terminal of the 2× gain amplifier is connected to the calibration terminal Vcal_P or Vcal_N of the comparator through the switch S int4 , the upper plate of the capacitor C int3 is connected to an output terminal, lower plates of all of the capacitors are connected to the ground, and the reset switch S int5 is connected in series with the output terminal and the ground for resetting an output voltage.

6. A calibration method for an offset calibration circuit applied to a comparator array, wherein the method is implemented based on the offset calibration circuit according to claim 1 , and the method comprises:
step 1: when a comparator starts the calibration, input terminals of the comparator VIP and VIN are both connected to a common-mode voltage Vcm, local calibration terminals Vcal_P and Vcal_N of the comparator and a global calibration voltage Vgcal are reset, and the comparator outputs first comparison results;
step 2: a local logic control circuit determines a calibration side according to the first comparison results of the comparator in the step 1, an integrator integrates the global calibration voltage, such that a voltage at the Vcal_P is increased by Vref, or a voltage at the Vcal_N is increased by Vref; and the comparator outputs second comparison results;
step 3: a global logic control circuit controls a global calibration voltage generation module, such that a global calibration voltage is reduced from Vref to

1
2

⁢
Vref

;

step 4: the local logic control circuit determines a calibration side according to the second comparison results of the comparator in the step 2, the integrator integrates the global calibration voltage Vgcal, such that a voltage at the Vcal_P is increased by

1
2

⁢
Vref

,

or a voltage at the Vcal_N is increased by

1
2

⁢
Vref

;

and the comparator outputs third comparison results; and
step 5: the operations in the steps 3 and 4 are repeated until the global calibration voltage Vgcal outputted by the global calibration voltage generation module is

Assignees

• Univ Jiangnan

Inventors

• Yu Zhiguo
• Zhou Hai
• Zhong Xiaoyu
• Gu Xiaofeng

Classifications

• H03M1/1023

  Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03K5/2481 Primary

  with at least one differential stage · CPC title

• H03K5/249 Primary

  using clock signals · CPC title