Display substrate, manufacturing method thereof, and display device

US12293725B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12293725-B2
Application numberUS-202318545797-A
CountryUS
Kind codeB2
Filing dateDec 19, 2023
Priority dateJun 4, 2020
Publication dateMay 6, 2025
Grant dateMay 6, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display substrate, a manufacturing method and a display device are provided. At least one of the plurality of shift register units in the scan driving circuit includes an output circuit including an output transistor and an output reset transistor; a length of the active layer of the output transistor/the output reset transistor in the first direction is a first length/a second length, and a sum thereof is an output active length; a smaller one of minimum width of the active layer of the output transistor and the output reset transistor in a second direction is a first output active width, the first direction intersects the second direction; a ratio of the output active length to the first output active width is within a first predetermined ratio range greater than or equal to 3 and less than or equal to 11.

First claim

Opening claim text (preview).

What is claimed is: 1. A display substrate comprising a scan driving circuit and a display area provided on a base substrate, wherein the scan driving circuit includes a plurality of shift register units, and at least one of the plurality of shift register units includes an output circuit, and the output circuit includes a first switch and a second switch; an active layer of the first switch and an active layer of the second switch are arranged along a first direction, a length of the active layer of the first switch in the first direction is a first length, and a length of the active layer of the second switch in the first direction is a second length, and a sum of the first length and the second length is an output active length; a smaller one of a minimum width of the active layer of the first switch in a second direction and a minimum width of the active layer of the second switch in the second direction is a first output active width, the first direction intersects the second direction; a ratio of the output active length to the first output active width is within a first predetermined ratio range; the first predetermined ratio range is greater than or equal to 3 and less than or equal to 11; wherein the first predetermined ratio is 3, 4, 5, 6, 7, 8, 9, 10, or 11. 2. The display substrate according to claim 1 , wherein the first output active width is greater than or equal to 12 microns and less than or equal to 40 microns. 3. The display substrate according to claim 1 , wherein the active layer of the first switch and the active layer of the second switch are formed by a continuous first semiconductor layer; the first semiconductor layer extends along the first direction; a length of the first semiconductor layer in the first direction is the output active length; a minimum length of the first semiconductor layer in the second direction is the first output active width. 4. The display substrate according to claim 1 , wherein the at least one shift register unit further includes an output reset capacitor; the scan driving circuit further includes a first voltage signal line; a first electrode plate of the output reset capacitor is coupled to a gate electrode of the second switch; a second electrode plate of the output reset capacitor is coupled to the first voltage signal line; the second electrode plate of the output reset capacitor extends along the second direction; the first voltage signal line and the output reset capacitor are both located on a side of the output circuit away from the display area. 5. The display substrate according to claim 1 , wherein the scan driving circuit further includes a first voltage signal line and a second voltage signal line; the at least one shift register unit further includes an output reset capacitor; the output circuit is located between the first voltage signal line and the second voltage signal line, the first voltage signal line is located on a side of the output circuit away from the display area, and the second voltage signal line is located on a side of the output circuit close to the display area; the first electrode of the first switch is coupled to the second voltage signal line; the first electrode of the second switch is coupled to the second electrode plate of the output reset capacitor, wherein both the first voltage signal line and the second voltage signal line extend along the first direction; a minimum distance in the second direction between an edge of an orthographic projection of the active layer of the first switch on the base substrate and an edge of an orthographic projection of the second voltage signal line on the base substrate is a first predetermined distance; wherein the first predetermined distance is greater than or equal to 10 microns and less than or equal to 15 microns. 6. The display substrate according to claim 1 , wherein the scan driving circuit further includes a second voltage signal line, and the at least one shift register unit further includes a signal output line; the second voltage signal line extends along the first direction, and the second voltage signal line is located on a side of the output circuit close to the display area; the signal output line includes a first output line portion extending in the first direction; the first output line portion is coupled to a second electrode of the first switch through a plurality of first signal line via holes arranged in a first signal line overlap area, and the first output line portion is coupled to the second electrode of the second switch through a plurality of second signal line via holes in a second signal line overlap area, the plurality of first signal line via holes are arranged in sequence along the first direction, and the plurality of second signal line via holes are arranged in sequence along the first direction; the first signal line overlap area is an overlap area between an orthographic projection of the first output line portion on the base substrate and an orthographic projection of a first source-drain metal pattern on the base substrate, the first source-drain metal pattern includes the second electrode of the first switch; the second signal line overlap area is an overlap area between the orthographic projection of the first output line portion on the base substrate and an orthographic projection of a second source-drain metal pattern on the base substrate, the second source-drain metal pattern includes the second electrode of the second switch; the first output line portion is located between the output circuit and the second voltage signal line. 7. The display substrate according to claim 1 , wherein the scan driving circuit further includes a second voltage signal line, and the at least one shift register unit further includes a signal output line; the signal output line includes a first output line portion and at least one second output line portion that are coupled to each other; the second voltage signal line and the first output line portion extend in a first direction, and the first output line portion is located between the second voltage signal line and the output circuit; the second output line portion extends along the second direction; the second output line portion is used for coupling with a pixel circuit in the display area; the first output line portion and the output circuit are located on a side of the second voltage signal line away from the display area. 8. The display substrate according to claim 1 , wherein the minimum width of the active layer of the first switch in the second direction is smaller than or equal to the minimum width of the active layer of the second switch in the second direction, wherein the at least one shift register unit further comprises an output capacitor; a first electrode plate of the output capacitor is coupled to the gate electrode of the first switch; an orthographic projection of a second electrode plate of the output capacitor on the base substrate is within an orthographic projection of the first electrode plate of the output capacitor on the base substrate; the output capacitor is located on a side of the first switch away from the display area; wherein a shape of the second electrode plate of the output capacitor is an L shape. 9. The display substrate according to claim 1 , wherein the at least one shift register unit further comprises a first transistor; the first transistor includes a first active pattern; the first active pattern extends in a second direction; the first transistor is located on a side of the output circuit away from the display area. 10. The display substrate according to claim 1 , wherein the at least one shift register unit further includes a fi

Assignees

Inventors

Classifications

  • H10K59/131Primary

    Interconnections, e.g. wiring lines or terminals · CPC title

  • using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

  • Details of a shift registers arranged for use in a driving circuit · CPC title

  • G09G3/3266Primary

    Details of drivers for scan electrodes · CPC title

  • Layout of electrodes and connections · CPC title

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Frequently asked questions

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What does patent US12293725B2 cover?
A display substrate, a manufacturing method and a display device are provided. At least one of the plurality of shift register units in the scan driving circuit includes an output circuit including an output transistor and an output reset transistor; a length of the active layer of the output transistor/the output reset transistor in the first direction is a first length/a second length, and a …
Who is the assignee on this patent?
Chengdu Boe Optoelect Tech Co, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/131. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 06 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).