Semiconductor device, data generation methods used for the same, and method of controlling the same

Patent metadata

Field	Value
Publication number	US-12293162-B2
Application number	US-202117358579-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jul 2, 2020
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

A semiconductor device includes: a local memory outputting a plurality of pieces of weight data in parallel; a plurality of product-sum operation units corresponding to the plurality of pieces of weight data; and a plurality of unit selectors corresponding to the product-sum operations units, supplied with a plurality of pieces of input data in parallel, selecting the one piece of input data from the supplied plurality of pieces of input data according to a plurality of pieces of additional information each indicating a position of the input data to be calculated with the corresponding product-sum arithmetic unit calculator in the pieces of input data, and outputting the selected input data. Each of the plurality of product-sum arithmetic units performs a product-sum operation between the weight data different from each other in the plurality of pieces of weight data and the input data outputted from the corresponding unit selector.

First claim

What is claimed is:

1. A semiconductor device comprising:
a memory outputting a plurality of pieces of first data in parallel;
a parallel arithmetic circuit including:
a plurality of product-sum arithmetic circuits corresponding to the plurality of pieces of first data; and
a plurality of selectors corresponding to the plurality of product-sum arithmetic circuits, supplied with a plurality of pieces of second data in parallel,

wherein the parallel arithmetic circuit is configured to perform:
an omitting step of omitting, in a plurality of pieces of original data arranged in a matrix, one piece of original data corresponding to a predetermined value from the plurality of pieces of original data arranged in a column;
a compressing step of being filled with the plurality of pieces of original data on an upper row arranged in the same column as that of the original data omitted in the omitting step instead of the omitted original data; and
an additional information generating step of generating, in the plurality of pieces of second data, additional information indicating a position of second data to be computed with the plurality of pieces of original data not omitted in the omitting step,

wherein the plurality of pieces of original data arranged in the same row are generated as the plurality of pieces of first data,
wherein, in the plurality of pieces of original data arranged in the matrix, a small value among the plurality of pieces of original data arranged in the same column is set as a threshold value, and a value smaller than the threshold value is set as the predetermined value,
wherein, in the plurality of pieces of original data arranged in the matrix, the threshold value in each column is set so that the pieces of original data arranged in each column are equal to each other in number,
wherein the plurality of selectors selects one piece of second data from the supplied plurality of pieces of second data according to the additional information, and outputs the selected one piece of second data, and
wherein each of the plurality of product-sum arithmetic circuits performs a product-sum operation between the first data different from each other in the plurality of first data and the second data outputted from the corresponding selectors.

2. The semiconductor device according to claim 1 ,
wherein the plurality of pieces of first data and a plurality of pieces of additional information comprising the addition information are stored in the memory, and the memory continuously outputs the plurality of pieces of first data different from each other and the plurality of pieces of additional information in a first period, and
wherein the plurality of pieces of second data are continuously supplied to the plurality of selectors in the first period.

3. The semiconductor device according to claim 2 , wherein a plurality of pieces of first data compressed to reduce data corresponding to a numerical value 0 are stored in the memory.

4. The semiconductor device according to claim 3 , wherein a plurality of pieces of second data different from the plurality of pieces of second data supplied in the first period are supplied to the plurality of selectors in a second period following the first period.

5. A data generation method of generating a plurality of pieces of first data used for a parallel arithmetic circuit,
wherein the parallel arithmetic circuit including:
a plurality of product-sum arithmetic circuits corresponding to the plurality of pieces of first data; and
a plurality of selectors corresponding to the plurality of product-sum arithmetic circuits, supplied with a plurality of pieces of second data in parallel, selecting second data from the supplied plurality of pieces of second data according to additional information, and outputting the selected second data to the corresponding product-sum arithmetic circuits,

wherein the data generation method comprising:
an omitting step of omitting, in a plurality of pieces of original data arranged in a matrix, one piece of original data corresponding to a predetermined value from the plurality of pieces of original data arranged in a column;
a compressing step of being filled with the plurality of pieces of original data on an upper row arranged in the same column as that of the original data omitted in the omitting step instead of the omitted original data; and
an additional information generating step of generating, in the plurality of pieces of second data, additional information indicating a position of second data to be computed with the plurality of pieces of original data not omitted in the omitting step, and

wherein the plurality of pieces of original data arranged in the same row are generated as the plurality of pieces of first data,
wherein, in the plurality of pieces of original data arranged in the matrix, a small value among the plurality of pieces of original data arranged in the same column is set as a threshold value, and a value smaller than the threshold value is set as the predetermined value, and
wherein, in the plurality of pieces of original data arranged in the matrix, the threshold value in each column is set so that the pieces of original data arranged in each column are equal to each other in number.

6. The data generation method according to claim 5 , wherein the predetermined value is a numerical value 0.

7. The data generation method according to claim 5 ,
wherein the matrix in which the plurality of pieces of original data are arranged is composed of a plurality of matrices, and each time the plurality of pieces of second data supplied to the selectors vary, the plurality of pieces of first data from the different matrices are supplied to the plurality of product-sum arithmetic circuits,
wherein the data generation method further comprises:
an important degree setting step of setting an important degree to each row of the plurality of matrices; and
a row number setting step of obtaining, in the plurality of matrices, the number of rows to be left for each matrix based on the important degree set in the important degree setting step according to a specified value for specifying the number of rows to be left, and

wherein the predetermined value is set so that the number of rows obtained in the row number setting step is maintained for each column of the matrices.

8. A data generation method of generating a plurality of pieces of first data used for a parallel arithmetic circuit,
wherein the parallel arithmetic circuit including:
a plurality of product-sum arithmetic circuits corresponding to the plurality of pieces of first data; and
a plurality of selectors corresponding to the plurality of product-sum arithmetic circuits, supplied with a plurality of pieces of second data in parallel, selecting second data from the supplied plurality of pieces of second data according to additional information, and outputting the selected second data to the corresponding product-sum arithmetic circuits,

wherein the data generation method comprising:
an omitting step of omitting, in a plurality of pieces of original data arranged in a matrix, one piece of original data corresponding to a predetermined value from the plurality of pieces of original data arranged in a column;
a compressing step of being filled with the plurality of pieces of original data on an upper row arranged in the same column as that of the original data omitted in the omitting step instead of the omitted original data; and
an additional information generating step of generating, in the plurality of pieces of second data, additional information indicating a position of second data to be computed with the plurality of pieces of original data not omitted in the omitting step,

wherein

Assignees

• Renesas Electronics Corp

Inventors

• Fujii Taro
• Togawa Katsumi
• Tanaka Teruhito
• Toi Takao

Classifications

• G06N3/082

  modifying the architecture, e.g. adding, deleting or silencing nodes or connections · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title

• G06F2207/4824

  Neural networks · CPC title

• G06N3/08

  Learning methods · CPC title