Fabric-based root-of-trust

Patent metadata

Field	Value
Publication number	US-12292979-B2
Application number	US-202218051167-A
Country	US
Kind code	B2
Filing date	Oct 31, 2022
Priority date	Oct 31, 2022
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

A method of creating a root-of-trust (RoT) within a network fabric may include powering on a network interface card (NIC) baseboard management controller (BMC) (NIC BMC), booting up a NIC via the NIC BMC, obtaining an address for the NIC, verifying an identity of the NIC at a fabric trust identity server using a key obtained from a secure vault communicatively coupled to the NIC BMC, verifying with the fabric trust identity server a number of images of a host device residing in the NIC based at least in part on the identity of the NIC being verified, and instructing a platform BMC to boot up the host device based at least in part on the number of images of the host device being verified.

First claim

What is claimed is:

1. A method of creating a root-of-trust (ROT) within a network fabric, comprising:
powering on a network interface card (NIC) baseboard management controller (BMC) (NIC BMC) located on a NIC;
booting up a NIC via the NIC BMC;
obtaining an address for the NIC;
verifying an identity of the NIC at a fabric trust identity server using a key obtained from a secure vault communicatively coupled to the NIC BMC;
verifying with the fabric trust identity server a number of images of a host device residing in the NIC based at least in part on the identity of the NIC being verified; and
instructing a platform BMC to boot up the host device based at least in part on the number of images of the host device being verified.

2. The method of claim 1 , further comprising authenticating the NIC as to an advanced reduced instruction set computer (RISC) machine (ARM) using the key obtained from the secure vault communicatively coupled to the NIC BMC.

3. The method of claim 2 , further comprising instructing the NIC, with the NIC BMC, to boot up a number of ARM cores associated with the ARM.

4. The method of claim 1 , further comprising provisioning the number of images of the host device for execution on the host device.

5. The method of claim 1 , wherein the secure vault comprises a System-on-Chip (SoC) electrical programmable fuse (eFuse).

6. The method of claim 1 , wherein the key of the secure vault is secured within the secure vault at a time of manufacture.

7. The method of claim 1 , wherein the platform BMC maintains the host device in a reset state until the NIC BMC instructs the platform BMC to boot up the host device.

8. The method of claim 1 , further comprising periodically exchanging an authentication message between the NIC BMC and the platform BMC to ensure that tampering of the platform BMC has not occurred.

9. A non-transitory computer-readable medium storing instructions that, when executed, causes a processor to perform operations, comprising:
powering on a network interface card (NIC) baseboard management controller (BMC) (NIC BMC) located on a NIC;
booting up a NIC via the NIC BMC;
obtaining an address for the NIC;
verifying an identity of the NIC at a fabric trust identity server using a key obtained from a secure vault communicatively coupled to the NIC BMC;
verifying with the fabric trust identity server a number of images of a host device residing in the NIC based at least in part on the identity of the NIC being verified; and
instructing a platform BMC to boot up the host device based at least in part on the number of images of the host device being verified.

10. The non-transitory computer-readable medium of claim 9 , the operations further comprising authenticating the NIC as to an advanced reduced instruction set computer (RISC) machine (ARM) using the key obtained from the secure vault communicatively coupled to the NIC BMC.

11. The non-transitory computer-readable medium of claim 10 , the operations further comprising instructing the NIC, with the NIC BMC, to boot up a number of ARM cores associated with the ARM.

12. The non-transitory computer-readable medium of claim 9 , the operations further comprising provisioning the number of images of the host device for execution on the host device.

13. The non-transitory computer-readable medium of claim 9 , wherein the secure vault comprises a System-on-Chip (SoC) electrical programmable fuse (eFuse).

14. The non-transitory computer-readable medium of claim 9 , wherein the key of the secure vault is secured within the secure vault at a time of manufacture.

15. The non-transitory computer-readable medium of claim 9 , wherein the platform BMC maintains the host device in a reset state until the NIC BMC instructs the platform BMC to boot up the host device.

16. The non-transitory computer-readable medium of claim 9 , the operations further comprising periodically exchanging an authentication message between the NIC BMC and the platform BMC to ensure that tampering of the platform BMC has not occurred.

17. A computing device comprising:
a processor; and
a non-transitory computer-readable media storing instructions that, when executed by the processor, causes the processor to perform operations comprising:
powering on a network interface card (NIC) baseboard management controller (BMC) (NIC BMC) located on a NIC;
booting up a NIC via the NIC BMC;
obtaining an address for the NIC;
verifying an identity of the NIC at a fabric trust identity server using a key obtained from a secure vault communicatively coupled to the NIC BMC;
verifying with the fabric trust identity server a number of images of a host device residing in the NIC based at least in part on the identity of the NIC being verified; and
instructing a platform BMC to boot up the host device based at least in part on the number of images of the host device being verified.

18. The computing device of claim 17 , the operations further comprising:
authenticating the NIC as to an advanced reduced instruction set computer (RISC) machine (ARM) using the key obtained from the secure vault communicatively coupled to the NIC BMC;
instructing the NIC, with the NIC BMC, to boot up a number of ARM cores associated with the ARM;
provisioning the number of images of the host device for execution on the host device.

19. The computing device of claim 17 , wherein the NIC is a smart NIC (SNIC).

20. The computing device of claim 17 , the operations further comprising periodically exchanging an authentication message between the NIC BMC and the platform BMC to ensure that tampering of the platform BMC has not occurred.

Assignees

• Cisco Tech Inc

Inventors

• Dvorkin Mike
• Kar Chakradhar
• Banerjee Ayan

Classifications

• G06F2221/034

  Test or assess a computer or a system · CPC title

• G06F9/4406

  Loading of operating system · CPC title

• G06F21/44

  Program or device authentication · CPC title

• H04L63/0876

  based on the identity of the terminal or configuration, e.g. MAC address, hardware or software configuration or device fingerprint · CPC title

• G06F21/575 Primary

  Secure boot · CPC title