Dynamic load balancing for multi-core computing environments

Patent metadata

Field	Value
Publication number	US-12289239-B2
Application number	US-202318154619-A
Country	US
Kind code	B2
Filing date	Jan 13, 2023
Priority date	Sep 11, 2019
Publication date	Apr 29, 2025
Grant date	Apr 29, 2025

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

First claim

What is claimed is:

1. A semiconductor die comprising:
a first core and a second core; and
circuitry in the semiconductor die, the circuitry separate from the first core and the second core, the circuitry to:
assign the first core to process first data packets of a data flow, the first core to execute one or more operations on the first data packets to produce processed first data packets;
assign the second core to process second data packets of the data flow based on a size of the data flow, the second core to execute the one or more operations on the second data packets to produce processed second data packets; and
re-order the processed first data packets and the processed second data packets to produce a processed data flow.

2. The semiconductor die of claim 1 , wherein the first data packets and the second data packets are to be received from a first network interface card, and the circuitry is to aggregate the processed first data packets and the processed second data packets after being re-ordered in preparation for distribution to a second network interface card.

3. The semiconductor die of claim 1 , wherein the semiconductor die includes a third core, and the circuitry is to assign the third core to process third data packets of a second data flow.

4. The semiconductor die of claim 1 , wherein the circuitry is to assign the second core to process the second data packets of the data flow based on a comparison of the size of the data flow to a threshold.

5. The semiconductor die of claim 1 , wherein the data flow corresponds to a single session associated with a network connection, and the circuitry is to assign the second core to process the second data packets based on a duration of the network connection.

6. The semiconductor die of claim 5 , wherein the circuitry is to assign the second core to process the second data packets based on a comparison of the duration of the network connection to a threshold.

7. The semiconductor die of claim 1 , wherein the semiconductor die includes a third core, and the circuitry is to assign the third core to process the second data packets of the data flow based on a bandwidth associated with the second core.

8. The semiconductor die of claim 7 , wherein the circuitry is to assign the third core to process the second data packets of the data flow based on a comparison of the bandwidth associated with the second core to a threshold.

9. The semiconductor die of claim 1 , wherein the first core and the second core are included in a plurality of cores and the circuitry is to select ones of the plurality of cores based on at least one of an atomic scheduling or an ordered scheduling to distribute processing of the data flow.

10. The semiconductor die of claim 1 , wherein the data flow includes ciphertext, and the one or more operations include one or more cryptographic operations.

11. A method comprising:
assigning, with circuitry of a semiconductor die, first data packets of a data flow to a first core of the semiconductor die, the first core to execute one or more operations on the first data packets to produce processed first data packets, the circuitry of the semiconductor die separate from the first core and a second core of the semiconductor die;
assigning, with the circuitry, second data packets of the data flow to the second core based on a size of the data flow, the second core to execute the one or more operations on the second data packets to produce processed second data packets; and
re-ordering the processed first data packets and the processed second data packets to produce a processed data flow.

12. The method of claim 11 , further including:
receiving the first data packets and the second data packets from a first network interface card; and
aggregating the processed first data packets and the processed second data packets after being re-ordered in preparation for distribution to a second network interface card.

13. The method of claim 11 , wherein the semiconductor die includes a third core, and further including assigning the third core to process third data packets of a second data flow.

14. The method of claim 11 , wherein the assigning of the second core is based on a comparison of the size of the data flow to a threshold.

15. The method of claim 11 , wherein the data flow corresponds to a single session associated with a network connection, and the assigning of the second core is based a duration of the network connection.

16. The method of claim 15 , wherein the assigning of the second core is based on a comparison of the duration of the network connection to a threshold.

17. The method of claim 11 , wherein the semiconductor die includes a third core, and further including assigning the third core to process the second data packets of the data flow based on a bandwidth associated with the second core.

18. The method of claim 17 , wherein the assigning of the third core is based on a comparison of the bandwidth associated with the second core to a threshold.

19. An apparatus comprising:
a first core and a second core of a processor; and
circuitry in a die of the processor, the circuitry separate from the first core and the second core, the die including the first core, the second core, and the circuitry, the circuitry to:
enqueue an identifier in a queue in the circuitry, the identifier to reference a data packet obtained by a network interface card;
dequeue the identifier to the first core to cause the first core to execute a first operation on the data packet;
enqueue the identifier in the queue in response to obtaining an indication of completion of the first operation;
dequeue the identifier to the first core or the second core to cause the first core or the second core to execute a second operation on the data packet different from the first operation; and
distribute the data packet.

20. The apparatus of claim 19 , wherein the first operation is a decryption operation of an Internet Protocol security (IPsec) application and the second operation is an encryption operation of the IPsec application.

Assignees

• Intel Corp

Inventors

• Palermo Stephen
• Chaddick Bradley
• Eads Gage
• Ganguli Mrittika
• Khade Abhishek
• Layek Abhirupa
• Maini Sarita
• Mcdonnell Niall
• Shah Rahul
• Shah Shrikant
• Burroughs William
• Sonnier David

Classifications

• H04L47/6275

  based on priority · CPC title

• H04L47/6255

  queue load conditions, e.g. longest queue first · CPC title

• H04L47/624

  Altering the ordering of packets in an individual queue · CPC title

• H04L47/62

  characterised by scheduling criteria · CPC title

• H04L47/125 Primary

  by balancing the load, e.g. traffic engineering · CPC title