Graphics system with additional context

US12288287B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12288287-B2
Application numberUS-202418436688-A
CountryUS
Kind codeB2
Filing dateFeb 8, 2024
Priority dateApr 17, 2017
Publication dateApr 29, 2025
Grant dateApr 29, 2025

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.

First claim

Opening claim text (preview).

What is claimed is: 1. A head mounted display (HMD) system, comprising: a memory; logic communicatively coupled to the memory, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality logic hardware, the logic communicatively coupled to the memory to: receive, with a low precision compute engine, a command from a first command stream; receive with the low precision compute engine, a frame from a graphics processor, wherein the graphics processor is associated with a second command stream; and execute, with the low precision compute engine, a foveated render operation associated with a time warp operation on the frame to account for an increased radius of the time warp operation based on the command from the first command stream. 2. The HMD system of claim 1 , wherein the logic communicatively coupled to the memory is to execute the time warp operation. 3. The HMD system of claim 1 , wherein the low precision compute engine is a fixed point image processor that includes compute units configured to execute integer arithmetic. 4. The HMD system of claim 1 , wherein the low precision compute engine is a fixed function engine. 5. The HMD system of claim 1 , wherein the low precision compute engine is a programmable fixed point general purpose unit. 6. The HMD system of claim 1 , wherein the HMD system further comprises a memory interface that is shared between the low precision compute engine and the graphics processor. 7. The HMD system of claim 1 , wherein the logic communicatively coupled to the memory is to execute space warp and machine learning with the low precision compute engine. 8. At least one non-transitory computer readable storage medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to: receive, with a low precision compute engine, a command from a first command stream; receive with the low precision compute engine, a frame from a graphics processor, wherein the graphics processor is associated with a second command stream; and execute, with the low precision compute engine, a foveated render operation associated with a time warp operation on the frame to account for an increased radius of the time warp operation based on the command from the first command stream. 9. The at least one non-transitory computer readable storage medium of claim 8 , wherein the instructions when executed by the computing device, cause the computing device to execute the time warp operation. 10. The at least one non-transitory computer readable storage medium of claim 8 , wherein the low precision compute engine is a fixed point image processor that includes compute units configured to execute integer arithmetic. 11. The at least one non-transitory computer readable storage medium of claim 8 , wherein the low precision compute engine is a fixed function engine. 12. The at least one non-transitory computer readable storage medium of claim 8 , wherein the low precision compute engine is a programmable fixed point general purpose unit. 13. The at least one non-transitory computer readable storage medium of claim 8 , wherein a memory interface is shared between the low precision compute engine and the graphics processor. 14. The at least one non-transitory computer readable storage medium of claim 8 , wherein the instructions when executed by the computing device, cause the computing device to execute space warp and machine learning with the low precision compute engine. 15. A method comprising: receiving, with a low precision compute engine, a command from a first command stream; receiving with the low precision compute engine, a frame from a graphics processor, wherein the graphics processor is associated with a second command stream; and executing, with the low precision compute engine, a foveated render operation associated with a time warp operation on the frame to account for an increased radius of the time warp operation based on the command from the first command stream. 16. The method of claim 15 , wherein the method further comprises executing the time warp operation. 17. The method of claim 15 , wherein the low precision compute engine is a fixed point image processor that includes compute units configured to execute integer arithmetic. 18. The method of claim 15 , wherein the low precision compute engine is a fixed function engine. 19. The method of claim 15 , wherein the low precision compute engine is a programmable fixed point general purpose unit, and wherein a memory interface is shared between the low precision compute engine and the graphics processor. 20. The method of claim 15 , further comprising executing space warp and machine learning with the low precision compute engine.

Assignees

Inventors

Classifications

  • G06F9/5027Primary

    the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

  • Texture mapping · CPC title

  • Constructive solid geometry [CSG] using solid primitives, e.g. cylinders, cubes · CPC title

  • Shading · CPC title

  • Using real world measurements to influence rendering · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US12288287B2 cover?
An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06F9/5027. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 29 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).