Out-of-order pixel shading and rasterization

Patent metadata

Field	Value
Publication number	US-12288283-B2
Application number	US-202117357403-A
Country	US
Kind code	B2
Filing date	Jun 24, 2021
Priority date	Jun 24, 2021
Publication date	Apr 29, 2025
Grant date	Apr 29, 2025

Abstract

Methods, systems and apparatuses may provide for technology that determines that a state of a plurality of primitives is associated with out-of-order execution. The plurality of primitives is associated with a raster order. The technology reorders the plurality of primitives from a raster order, and distributes one or more of pixel processing operations or rasterization operations associated with the plurality of primitives to load balance across one or more of a plurality of execution units of a graphics processor or a graphics pipeline of the graphics processor.

First claim

We claim:

1. A computing system comprising:
a display to present an image; and
a graphics processor coupled to the display, wherein the graphics processor includes logic coupled to one or more substrates, the logic to:
determine that a state of a plurality of primitives is to be associated with out-of-order execution, wherein the plurality of primitives is associated with a raster order;
reorder the plurality of primitives from the raster order;
distribute one or more of pixel processing operations or rasterization operations associated with the plurality of primitives to load balance across one or more of a plurality of execution units of the graphics processor or a graphics pipeline of the graphics processor;
determine a plurality of pixel values associated with the plurality of primitives;
emit a first pixel value of the plurality of pixel values associated with a first pixel location; and
after the first pixel value is emitted, emit a second pixel value of the plurality of pixel values associated with the first pixel location,
wherein the raster order indicates that the second pixel value is to be emitted before the first pixel value.

2. The computing system of claim 1 , wherein the logic coupled to the one or more substrates is to:
distribute one or more of the pixel processing operations or the rasterization operations associated with the plurality of primitives irrespective of screen space associated with the plurality of primitives.

3. The computing system of claim 2 , wherein the logic coupled to the one or more substrates is to:
in response to the state of the plurality of primitives being associated with the out-of-order execution, flush primitives that are associated with in-order execution from the one or more of the plurality of execution units or the graphics pipeline.

4. The computing system of claim 1 , wherein the logic coupled to the one or more substrates is to:
identify a hint from an application associated with the plurality of primitives; and
determine that the out-of-order execution is to be enabled based on the hint.

5. The computing system of claim 4 , wherein the logic coupled to the one or more substrates is to:
bypass the raster order to execute the out-of-order execution, wherein the raster order is determined by the application.

6. The computing system of claim 4 ,
wherein the first pixel value is associated with a first primitive of the plurality of primitives;
wherein the second pixel value is associated with a second primitive of the plurality of primitives; and
wherein the raster order indicates that the second primitive is to be emitted before the first primitive.

7. The computing system of claim 6 , wherein the logic coupled to the one or more substrates is to:
disable a dependency track operation that is to track dependencies between the plurality of pixel values.

8. The computing system of claim 1 , wherein the logic coupled to the one or more substrates is to:
distribute a geometric processing operation associated with the plurality of primitives to load balance across the one or more of the plurality of execution units or the graphics pipeline.

9. A semiconductor apparatus comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
determine that a state of a plurality of primitives is to be associated with out-of-order execution, wherein the plurality of primitives is associated with a raster order;
reorder the plurality of primitives from the raster order;
distribute one or more of pixel processing operations or rasterization operations associated with the plurality of primitives to load balance across one or more of a plurality of execution units of a graphics processor or a graphics pipeline of the graphics processor;
determine a plurality of pixel values associated with the plurality of primitives;
emit a first pixel value of the plurality of pixel values associated with a first pixel location; and
after the first pixel value is emitted, emit a second pixel value of the plurality of pixel values associated with the first pixel location,
wherein the raster order indicates that the second pixel value is to be emitted before the first pixel value.

10. The semiconductor apparatus of claim 9 , wherein the logic coupled to the one or more substrates is to:
distribute one or more of the pixel processing operations or the rasterization operations associated with the plurality of primitives irrespective of screen space associated with the plurality of primitives.

11. The semiconductor apparatus of claim 10 , wherein the logic coupled to the one or more substrates is to:
in response to the state of the plurality of primitives being associated with the out-of-order execution, flush primitives that are associated with in-order execution from the one or more of the plurality of execution units or the graphics pipeline.

12. The semiconductor apparatus of claim 9 , wherein the logic coupled to the one or more substrates is to:
identify a hint from an application associated with the plurality of primitives; and
determine that the out-of-order execution is to be enabled based on the hint.

13. The semiconductor apparatus of claim 12 , wherein the logic coupled to the one or more substrates is to:
bypass the raster order to execute the out-of-order execution, wherein the raster order is determined by the application.

14. The semiconductor apparatus of claim 12 ,
wherein the first pixel value is associated with a first primitive of the plurality of primitives;
wherein the second pixel value is associated with a second primitive of the plurality of primitives; and
wherein the raster order is to indicate that the second primitive is to be emitted before the first primitive.

15. The semiconductor apparatus of claim 14 , wherein the logic coupled to the one or more substrates is to:
disable a dependency track operation that is to track dependencies between the plurality of pixel values.

16. The semiconductor apparatus of claim 9 , wherein the logic coupled to the one or more substrates is to:
distribute a geometric processing operation associated with the plurality of primitives to load balance across the one or more of the plurality of execution units or the graphics pipeline.

17. The semiconductor apparatus of claim 9 , wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

18. A method comprising:
determining that a state of a plurality of primitives is associated with out-of-order execution, wherein the plurality of primitives is associated with a raster order;
reordering the plurality of primitives from the raster order;
distributing one or more of pixel processing operations or rasterization operations associated with the plurality of primitives to load balance across one or more of a plurality of execution units of a graphics processor or a graphics pipeline of the graphics processor;
determining a plurality of pixel values associated with the plurality of primitives;
emitting a first pixel value of the plurality of pixel values associated with a first pixel location; and
after the first pixel value is emitted, emitting a second pixel value of the plurality of pixel values associated with the first pixel location,
wherein the raster order indicates that the second pixel va

Assignees

• Intel Corp

Inventors

• Surti Prasoonkumar
• Garcia Pabon Jorge
• Gierach John

Classifications

• G06T15/10

  Geometric effects · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F9/5083

  Techniques for rebalancing the load in a distributed system · CPC title

• G06T15/83

  Phong shading · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title