Integrated circuits (IC) chips including throttle request accumulate circuits for controlling power consumed in processing circuits and related methods

Patent metadata

Field	Value
Publication number	US-12287688-B2
Application number	US-202418623217-A
Country	US
Kind code	B2
Filing date	Apr 1, 2024
Priority date	Jun 22, 2023
Publication date	Apr 29, 2025
Grant date	Apr 29, 2025

Abstract

The processor-based system includes a throttle request accumulate circuit to receive throttle requests, determine a highest or most aggressive throttle value among the throttle requests, and generate a throttle control signal configured to throttle activity in the plurality of processing circuits. Throttle requests have throttle values corresponding to a reduction in activity in at least a portion of the plurality of processing circuits and may correspond to a particular number of cycles of reduced activity in a window of cycles. In addition to reducing response time to local events or conditions compared to waiting for a hierarchical response, the throttle request accumulate circuit accumulates throttle requests from all circuits that adjust or throttle activity in the plurality of processing circuits, and ensures that the net effective throttle controlling activity in the processing circuits at any given time is based on the highest throttle value of those accumulated throttle requests.

First claim

What is claimed is:

1. An integrated circuit (IC) chip comprising a processor-based system, the processor-based system comprising:
a first throttle request accumulate circuit configured to:
receive a plurality of throttle requests each comprising a first throttle value representing a first number X in a range of numbers from zero (0) to a second number Y; and
in each cycle of a clock signal, generate a throttle control signal comprising a second throttle value comprising a highest first throttle value among the plurality of throttle requests; and

first digital processing circuits configured to:
operate in response to the clock signal;
receive the throttle control signal; and
suspend operating in X cycles among Y+1 consecutive cycles of the clock signal in response to the throttle control signal.

2. The IC chip of claim 1 , wherein:
the first digital processing circuits are further configured to operate in response to the clock signal in (Y+1)−X cycles among the Y+1 consecutive cycles of the clock signal.

3. The IC chip of claim 1 , wherein the first digital processing circuits configured to suspend operation in the X cycles of the clock signal comprises the first digital processing circuits being configured to gate the clock signal to prevent transition of signal states in at least a portion of the first digital processing circuits in the X cycles.

4. The IC chip of claim 1 , the first throttle request accumulate circuit further configured to change the second throttle value of the throttle control signal in response to an indication of a change to the first throttle value of one of the plurality of throttle requests.

5. The IC chip of claim 1 , the processor-based system further comprising a plurality of leaf nodes, each comprising:
second digital processing circuits; and
a second throttle request accumulate circuit comprising throttle input interfaces, each configured to receive a throttle request;
wherein:
the second digital processing circuits of a first leaf node of the plurality of leaf nodes comprises the first digital processing circuits; and
the second throttle request accumulate circuit of the first leaf node comprises the first throttle request accumulate circuit.

6. The IC chip of claim 5 , wherein each of the throttle input interfaces in the second throttle request accumulate circuit of each of the plurality of leaf nodes comprises:
a throttle request input configured to receive a throttle request;
a target ID input configured to receive a target leaf node identifier; and
a throttle value valid input configured to receive a valid indication indicating the throttle request received on the throttle request input and the target leaf node identifier received on the target ID input in a first cycle of the clock signal are valid.

7. The IC chip of claim 5 , each leaf node of the plurality of leaf nodes further comprising:
a current change (di/dt) circuit configured to generate:
a di/dt throttle request in response to determining that a rate of change of electrical current provided to the leaf node exceeds a current change threshold;

wherein the throttle request received in one of the throttle input interfaces of the second throttle request accumulate circuit in the leaf node comprises the di/dt throttle request.

8. The IC chip of claim 7 , the di/dt circuit configured to generate the di/dt throttle request comprising:
a third throttle value in response to determining that a first rate of change of electrical current in the leaf node exceeds a first current change threshold; and
a fourth throttle value, higher than the third throttle value, in response to determining that a second rate of change of electrical current in the leaf node exceeds a second current change threshold higher than the first current change threshold.

9. The IC chip of claim 6 , the processor-based system further comprising a thermal sensor configured to:
detect a temperature in a region of the IC chip;
generate a thermal power event comprising a throttle request based on the temperature detected; and
provide, to one of the throttle input interfaces of the second throttle request accumulate circuit in each leaf node of the plurality of leaf nodes, a leaf node identifier corresponding to the leaf node.

10. The IC chip of claim 6 , the processor-based system further comprising a regional activity management (RAM) circuit, the RAM circuit configured to:
receive information on electrical current or power provided to the plurality of leaf nodes; and
provide a RAM throttle request comprising a throttle request based on the information received to one of the throttle input interfaces of the second throttle request accumulate circuit in the plurality of leaf nodes.

11. The IC chip of claim 6 , the processor-based system further comprising a firmware control circuit configured to generate a firmware throttle request comprising a throttle request based on activity one of the throttle input interfaces of the second throttle request accumulate circuit in the plurality of leaf nodes, wherein the firmware throttle request is provided to one of the throttle input interfaces of the second throttle request accumulate circuit in each leaf node of the plurality of leaf nodes.

12. The IC chip of claim 1 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

13. A method in an integrated circuit (IC) chip comprising a processor-based system, the method comprising:
receiving, in a first throttle request accumulate circuit, a plurality of throttle requests each comprising a first throttle value representing a first number X in a range of numbers from zero (0) to a second number Y;
in each cycle of a clock signal, generating a throttle control signal comprising a second throttle value comprising a highest first throttle value among the plurality of throttle requests;
operating first digital processing circuits in response to the clock signal;
receiving, in the first digital processing circuits, the throttle control signal; and
suspending operating of the first digital processing circuits in X cycles among Y+1 consecutive cycles of the clock signal in response to the throttle control signal.

14. The method of claim 13 , further comprising:
operating the first digital processing circuits in response to the clock signal in (Y+1)−X cycles among the Y+1 consecutive cycles of the clock signal.

15. The method of claim 13 , wherein suspending operation in the X cycles of the clock signal comprises gating the clock signal to prevent transition of signal states in at least a portion of the first digital processing circuits in the X cycles.

16. The method of claim 13 , further comprising changing, in the first throttle request accumulate circuit, the second throttle value of the throttle control signal in response to an indica

Assignees

• Qualcomm Inc

Inventors

• KOORAPATI Sagar
• Chamarty Vinod
• Kirtane Gaurav Sanjeev
• Pari Pushkin Raj
• Makhija Nitin
• Naveh Alon

Classifications

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title