Semiconductor devices and methods of manufacturing semiconductor devices

Patent metadata

Field	Value
Publication number	US-12284834-B2
Application number	US-202418777737-A
Country	US
Kind code	B2
Filing date	Jul 19, 2024
Priority date	May 6, 2022
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

In an example, a semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of the first conductivity type over the semiconductor substrate. A well region of a second conductivity type is in the semiconductor region. A doped region of the first conductivity type is in the well region. A doped region of the second conductivity type is in the well region. A doped region of the second conductivity type is in the semiconductor substrate at a bottom side. A doped region of the first conductivity type is in the semiconductor substrate at the bottom side. A first conductor is at a top side of the semiconductor region and a second conductor is at the bottom side. In some examples, one or more of doped regions at the bottom side is a patterned doped region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a region of semiconductor material comprising:
a top side;
a bottom side opposite to the top side;
a semiconductor substrate characterized by a first conductivity type; and
a semiconductor region over the semiconductor substrate and characterized by the first conductivity type and a dopant concentration greater than that of the semiconductor substrate;

a well region in the semiconductor region and characterized by a second conductivity type opposite to the first conductivity type;
a first doped region in the well region and characterized by the first conductivity type;
a second doped region in the well region and characterized by the second conductivity type;
a third doped region in the semiconductor substrate at the bottom side and characterized by the second conductivity type, a first lateral side, and a second lateral side opposite to the first lateral side;
a fourth doped region in the semiconductor substrate at the bottom side and characterized by the first conductivity type, wherein:
the fourth doped region comprises a first portion and a second portion;
the first portion abuts a first lateral side of the third doped region; and
the second portion abuts the second lateral side of the third doped region;

a first conductor coupled to the first doped region and the second doped region at the top side; and
a second conductor coupled to the third doped region and the fourth doped region at the bottom side;
wherein:
the semiconductor device is configured as a dual-sided semiconductor-controlled rectifier (SCR) device.

2. The semiconductor device of claim 1 , wherein:
the fourth doped region is a patterned doped region;
the third doped region has a first width in a cross-sectional view;
the first portion and the second portion of the fourth doped region sum to a second width in the cross-sectional view; and
the first width is different than the second width.

3. The semiconductor device of claim 2 , wherein:
the first width is less than the second width.

4. The semiconductor device of claim 2 , wherein:
the first width is greater than the second width.

5. The semiconductor device of claim 2 , wherein:
the first width and the second width sum to a device width; and
the first width is between 40% to 60% of the device width.

6. The semiconductor device of claim 1 , wherein:
the semiconductor substrate has a thickness between 75 microns and 100 microns.

7. The semiconductor device of claim 1 , wherein:
the second doped region comprises two portions on opposing sides of the first doped region in a cross-sectional view; and
the two portions each abut one of the opposing sides of the first doped region.

8. The semiconductor device of claim 1 , further comprising:
a substrate having a die pad and leads, wherein the second conductor of the semiconductor device is coupled to the die pad, and the first conductor is coupled to the leads; and
a package body encapsulating the semiconductor device and at least portions of the substrate.

9. The semiconductor device of claim 8 , wherein:
the die pad comprises a metal; and
the second conductor is coupled to the die pad with a high thermal conductivity material.

10. The semiconductor device of claim 9 , wherein:
the second conductor has a thickness between about two (2) microns and about nine (9) microns.

11. The semiconductor device of claim 1 , wherein:
one or more of the semiconductor substrate or the semiconductor region comprise a IV-IV semiconductor material.

12. A semiconductor device, comprising:
a region of semiconductor material comprising:
a top side;
a bottom side opposite to the top side;
a semiconductor substrate characterized by a first conductivity type and a semiconductor substrate thickness; and
a semiconductor region over the semiconductor substrate and characterized by the first conductivity type and a higher peak dopant concentration than the semiconductor substrate;

a well region in the semiconductor region and characterized by a second conductivity type opposite to the first conductivity type;
a first doped region in the well region and characterized by the first conductivity type;
a second doped region in the well region laterally adjacent to the first doped region and characterized by the second conductivity type;
a third doped region in the semiconductor substrate at the bottom side and characterized by the second conductivity type;
a fourth doped region in the semiconductor substrate at the bottom side laterally adjacent to the third doped region and characterized by the first conductivity type;
an anode terminal coupled to the first doped region and the second doped region at the top side; and
a cathode terminal coupled to the third doped region and the fourth doped region at the bottom side;
wherein:
the semiconductor device comprises a device width in a cross-sectional view;
the third doped region comprises a first width in the cross-sectional view;
the fourth doped region comprises a second width in the cross-sectional view; and
the first width is between 40% and 60% of the device width.

13. The semiconductor device of claim 12 , wherein:
the fourth doped region is a patterned doped region; and
the semiconductor substrate thickness is between 70 microns and 140 microns.

14. The semiconductor device of claim 12 , wherein:
the fourth doped region comprises two portions each on opposing lateral sides of the third doped region;
the two portions of the fourth doped region sum to the second width; and
the second width is different than the first width.

15. The semiconductor device of claim 12 , wherein:
the semiconductor device is configured as a two-terminal dual-sided vertical semiconductor-controlled rectifier (SCR) device; and
the second width is pre-selected to adjust holding current of the SCR device to a predetermined level.

16. The semiconductor device of claim 12 , wherein:
the region of semiconductor material comprises a IV-IV semiconductor material.

17. A method of manufacturing a semiconductor device, comprising:
providing a region of semiconductor material comprising:
a top side;
a bottom side opposite to the top side;
a semiconductor substrate characterized by a first conductivity type and a semiconductor substrate thickness; and
a semiconductor region over the semiconductor substrate and characterized by the first conductivity type and a higher peak dopant concentration than the semiconductor substrate;

providing a well region in the semiconductor region and characterized by a second conductivity type opposite to the first conductivity type;
providing a first doped region in the well region and characterized by the first conductivity type;
providing a second doped region in the well region laterally adjacent to the first doped region and characterized by the second conductivity type;
providing a third doped region in the semiconductor substrate at the bottom side and characterized by the second conductivity type;
providing a fourth doped region in the semiconductor substrate at the bottom side laterally adjacent to the third doped region and characterized by the first conductivity type;
providing an anode terminal coupled to the first doped region and the second doped region at the top side; and
providing a cathode terminal coupled to the third doped region and the fourth doped region at the bottom side;
wherein:
the semiconductor device comprises a device width in a cross-sectional view;
the third doped region comp

Assignees

• Semiconductor Components Ind Llc

Inventors

• Johnson Derrick
• Chen Yupeng
• Wall Ralph N
• Griswold Mark

Classifications

• H10D84/859

  comprising both N-type and P-type wells, e.g. twin-tub · CPC title

• H10D18/00

  Thyristors · CPC title

• H10D62/206

  Cathode base regions of thyristors · CPC title

• H10D62/199

  Anode base regions of thyristors · CPC title

• H10D89/713 Primary

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title