Display panel and display device

Patent metadata

Field	Value
Publication number	US-12284830-B2
Application number	US-202318384584-A
Country	US
Kind code	B2
Filing date	Oct 27, 2023
Priority date	Dec 30, 2020
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

A display panel includes a base substrate, a first transistor and a second transistor. The first transistor and the second transistor are formed on the base substrate. The first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes silicon. The second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer includes an oxide semiconductor. A length of a channel region of the first transistor is L1. Along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1. The first transistor further includes a third gate electrode. Along the direction perpendicular to the base substrate, a distance between the third gate electrode and the first active layer is D3, and D1<D3.

First claim

What is claimed is:

1. A display panel, comprising:
a base substrate;
a first transistor and a second transistor; wherein:
the first transistor and the second transistor are formed on the base substrate; the first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; the first active layer includes silicon; the second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; and the second active layer includes an oxide semiconductor;
a length of a channel region of the first transistor is L1; and along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1;
the first transistor further includes a third gate electrode; and along the direction perpendicular to the base substrate, a distance between the third gate electrode and the first active layer is D3, wherein D1<D3; and
a length of a channel region of the second transistor is L2; along the direction perpendicular to the base substrate, a distance between the second gate electrode and the second active layer is D2; and

a pixel circuit and a drive circuit providing a drive signal for the pixel circuit, wherein the first transistor is included in the pixel circuit, the second transistor is included in one of the pixel circuit and the drive circuit, the first transistor is a drive transistor of the pixel circuit, and (D1/D2)<(L1/L2).

2. The display panel according to claim 1 , wherein:
the second transistor further includes a fourth gate electrode, and along the direction perpendicular to the base substrate, a distance between the fourth gate electrode and the second active layer is D4, and D2<D4;
a channel region of the second transistor defined by the second gate electrode is a second channel region, and a length of the second channel region is L2;
a channel region of the second transistor defined by the fourth gate electrode is a fourth channel region, and a length of the fourth channel region is L4; and
a second area S2=L2×D2, a fourth area S4=L4×D4, and S2<S4.

3. The display panel according to claim 2 , wherein:
a channel region of the first transistor defined by the first gate electrode is a first channel region, and a length of the first channel region is L1; and
a first area S1=L1×D1, and S4+S1>2S2.

4. The display panel according to claim 1 , wherein:
a channel region of the first transistor defined by the first gate electrode is a first channel region, and a length of the first channel region is L1;
a channel region of the first transistor defined by the third gate electrode is a third channel region, and a length of the third channel region is L3; and
a first area S 1 =L 1 ×D 1 , a third area S3=L3×D3, and S1<S3.

5. The display panel according to claim 1 , wherein:
the display panel is a foldable display panel which includes a bending axis extending along a first direction, wherein
an angle between a length direction of the channel region of the second transistor and the first direction is greater than 45 degrees, and an angle between a length direction of the channel region of the first transistor and the first direction is less than 45 degrees.

6. The display panel according to claim 5 , wherein:
the length direction of the channel region of the second transistor is perpendicular to the first direction; and
the length direction of the channel region of the first transistor is in parallel with the first direction.

7. The display panel according to claim 1 , wherein:
the pixel circuit includes a third transistor;
the third transistor includes a fifth gate electrode, a third active layer, a third source electrode, and a third drain electrode; and the third active layer includes an oxide semiconductor;
along the direction perpendicular to the base substrate, a distance between the fifth gate electrode and the third active layer is D5; a channel region of the third transistor defined by the fifth gate electrode is a fifth channel region; a length of the fifth channel region is L5; and a fifth area S5=L5×D5;
the third transistor further includes a sixth gate electrode; along the direction perpendicular to the base substrate, a distance between the sixth gate electrode and the third active layer is D6; and D5<D6; and
a channel region of the third transistor defined by the sixth gate electrode is a sixth channel region; a length of the sixth channel region is L6; a sixth area S6=L6×D6; and S5<S6.

8. The display panel according to claim 7 , wherein:
the second transistor is a switch transistor of the pixel circuit; and/or
the third transistor is a switch transistor of the pixel circuit.

9. A display panel, comprising:
a base substrate;
a first transistor and a second transistor; wherein:
the first transistor and the second transistor are formed on the base substrate; the first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; the first active layer includes silicon; the second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; and the second active layer includes an oxide semiconductor;
a length of a channel region of the first transistor is L1; and along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1; and

a length of a channel region of the second transistor is L2; along the direction perpendicular to the base substrate, a distance between the second gate electrode and the second active layer is D2; and
a pixel circuit and a drive circuit providing a drive signal for the pixel circuit, wherein the first transistor is included in the pixel circuit, the second transistor is included in one of the pixel circuit and the drive circuit, the first transistor is a drive transistor of the pixel circuit, and (D1/D2)<(L1/L2).

10. The display panel according to claim 9 , wherein:
the second transistor further includes a fourth gate electrode, and along the direction perpendicular to the base substrate, a distance between the fourth gate electrode and the second active layer is D4, and D2<D4;
a channel region of the second transistor defined by the second gate electrode is a second channel region, and a length of the second channel region is L2;
a channel region of the second transistor defined by the fourth gate electrode is a fourth channel region, and a length of the fourth channel region is L4; and
a second area S2=L2×D2, a fourth area S4=L4×D4, and S2<S4.

11. The display panel according to claim 10 , wherein:
a channel region of the first transistor defined by the first gate electrode is a first channel region, a length of the first channel region is L1, a first area S1=L1×D1, and (S4+S1)>2S2.

12. The display panel according to claim 9 , wherein:
the first transistor further includes a third gate electrode, and along the direction perpendicular to the base substrate, a distance between the third gate electrode and the first active layer is D3, and D1<D3;
a channel region of the first transistor defined by the first gate electrode is a first channel region, and a length of the first channel region is L1;
a channel region of the first transistor defined by the third gate electrode is a third channel region, and a length of the third channel region is L3; and
a first area S1=L1×D1, a third area S3=L3×D3, and S1<S3.

13. The display panel according to claim 9 , further comprising a third transistor, wherein:
the third transistor

Assignees

• Xiamen Tianma Micro Electronics Co Ltd

Inventors

• Lai Qingjun
• Zhu Yihua
• Yuan Yong
• An Ping
• Cao Zhaokeng

Classifications

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D86/431

  having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• G09G2300/0814

  used for selection purposes, e.g. logical AND for partial update · CPC title