Method for manufacturing TFT substrate and TFT substrate thereof

Patent metadata

Field	Value
Publication number	US-12283601-B2
Application number	US-202117621941-A
Country	US
Kind code	B2
Filing date	Nov 8, 2021
Priority date	Oct 29, 2021
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

The embodiments of the present application provide a method for manufacturing thin-film transistor (TFT) substrate and a TFT substrate thereof. A semi-finished substrate has a first region, a second region, and a third region. The semiconductor layer and the insulating layer of the semi-finished substrate are patterned under the shielding of the first etching barrier layer and the second etching barrier layer having different thickness, so that only the semiconductor layer in the second region is kept and causing the thickness of the insulating layer in the first region is greater than the thickness of the insulating layer in the third region.

First claim

What is claimed is:

1. A method for manufacturing thin-film transistor (TFT) substrate, comprising:
step B 1 : forming a photoresist layer on a semi-finished substrate, wherein the semi-finished substrate comprises a first metal layer, an insulating layer disposed on the first metal layer, and a semiconductor layer disposed on the insulating layer, the photoresist layer is disposed on the semiconductor layer, and the semi-finished substrate has a first region, a second region, and a third region;
step B 2 : patterning the photoresist layer to expose the semiconductor layer in the third region, where a remaining portion of the photoresist forms a first etching barrier layer corresponding to the first region and where another remaining portion of the photoresist forms a second etching barrier layer corresponding to the second region, wherein a thickness of the first etching barrier layer is less than a thickness of the second etching barrier layer;
step B 3 : etching the semiconductor layer in the third region under the shielding of the first etching barrier layer and the second etching barrier layer;
step B 4 : peeling off the first etching barrier layer to expose the semiconductor layer in the first region;
Step B 5 : etching the semiconductor layer and the insulating layer under the shielding of the second etching barrier layer to remove the semiconductor layer disposed corresponding to the first region, such that a thickness of the insulating layer in the third region is less than a thickness of the insulating layer in the first region.

2. The method for manufacturing TFT substrate as claimed in claim 1 , wherein the step of patterning the photoresist layer in the step B 2 comprises: performing a photolithography process to the photoresist layer under the shielding of a mask.

3. The method for manufacturing TFT substrate as claimed in claim 2 , wherein the photolithography process is performed by using ultraviolet light in the step B 2 .

4. The method for manufacturing TFT substrate as claimed in claim 3 , wherein the exposure volume of the photoresist layer ranges from 35 mJ to 45 mJ.

5. The method for manufacturing TFT substrate as claimed in claim 2 , wherein the material of the photoresist layer is a positive photoresist, the mask comprises a first pattern region disposed corresponding to the first region, a second pattern region disposed corresponding to the second region, and a third pattern region disposed corresponding to the third region, the transmittance of the first pattern region is greater than the transmittance of the second pattern region, and the transmittance of the first pattern region is less than the transmittance of the third pattern region.

6. The method for manufacturing TFT substrate as claimed in claim 5 , wherein the transmittance of the first pattern region is 40% to 50%, the transmittance of the second pattern region is 0% to 10%, and the transmittance of the third pattern region is 90% to 100%.

7. The method for manufacturing TFT substrate as claimed in claim 2 , wherein the material of the photoresist layer is a negative photoresist, the mask comprises a first pattern region disposed corresponding to the first region, a second pattern region disposed corresponding to the second region, and a third pattern region disposed corresponding to the third region, the transmittance of the first pattern region is less than the transmittance of the second pattern region, and the transmittance of the first pattern region is greater than the transmittance of the third pattern region.

8. The method for manufacturing TFT substrate as claimed in claim 7 , wherein the transmittance of the first pattern region is 50% to 60%, the transmittance of the second pattern region is 90% to 100%, and the transmittance of the third pattern region is 0% to 10%.

9. The method for manufacturing TFT substrate as claimed in claim 1 , wherein the thickness of the first etching barrier layer is 20% to 35% of the thickness of the second etching barrier layer in the step B 2 .

10. The method for manufacturing TFT substrate as claimed in claim 1 , wherein the thickness of the first etching barrier layer obtained in the step B 2 is 4000Å to 6000Å, and the thickness of the second etching barrier layer obtained in the step B 2 is 15000Å to 20000Å.

11. The method for manufacturing TFT substrate as claimed in claim 1 , wherein in the step B 3 , the semiconductor layer in the third region is etched by dry etching under the shielding of the first etching barrier layer and the second etching barrier layer.

12. The method for manufacturing TFT substrate as claimed in claim 1 , wherein the semiconductor layer of the third region is partially or completely etched away.

13. The method for manufacturing TFT substrate as claimed in claim 1 , wherein the step of peeling off the first etching barrier layer to expose the semiconductor layer in the first region in the step B 4 comprises: ashing the first etching barrier layer and the second etching barrier layer to remove the first etching barrier layer and reduce the thickness of the second etching barrier layer.

14. The method for manufacturing TFT substrate as claimed in claim 1 , wherein the semiconductor layer and the insulating layer are etched by dry etching under the shielding of the second etching barrier layer in the step B 5 .

15. The method for manufacturing TFT substrate as claimed in claim 1 , wherein the first metal layer comprises a first signal line and a gate electrode, the first signal line is disposed corresponding to the first region, and the gate electrode is disposed corresponding to the second region.

16. The method for manufacturing TFT substrate as claimed in claim 15 , further comprising:
step B 6 : peeling off the second etching barrier layer to expose the semiconductor layer in the second region.

17. The method for manufacturing TFT substrate as claimed in claim 16 , further comprising:
step B 7 : forming a second metal layer on the insulating layer and the semiconductor layer.

18. The method for manufacturing TFT substrate as claimed in claim 17 , wherein in the step B 7 , the second metal layer comprises a second signal line, a source electrode, and a drain electrode, the second signal line is disposed corresponding to the first region, and the source electrode and the drain electrode are disposed corresponding to the second region.

19. The method for manufacturing TFT substrate as claimed in claim 18 , wherein the first signal line comprises a scan line extending in a first direction and a storage capacitor line extending in a second direction, the second signal line comprises a data line extending in the second direction, and the first direction and the second direction are set in a present angle.

Assignees

• Huizhou China Star Optoelectronics Display Co Ltd
• Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Deng Yongqi
• Chai Li

Classifications

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/0231 Primary

  using masks, e.g. half-tone masks · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title