Data transmission circuit and memory device

Patent metadata

Field	Value
Publication number	US-12283339-B2
Application number	US-202217796745-A
Country	US
Kind code	B2
Filing date	Apr 18, 2022
Priority date	Aug 20, 2021
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

The disclosed data transmission circuit and a memory include a sense amplifier circuit, a first sub-discharge path, a second sub-discharge path, and a discharge adjustment unit. The sense amplifier circuit generate amplified signals based on two terminals. The first sub-discharge path, in the read state, discharges at the first terminal to the discharge terminal based on the first data line signal; the second sub-discharge path, in reading state, discharges at the second terminal to the discharge terminal based on the discharge adjustment signa. The discharge adjustment unit is electrically connected to the second sub-discharge path and the control signal, but is not connected to the first sub-discharge path, and is used for generating the discharge adjustment signal based on the control signal, to adjust the discharge capacity of the second sub-discharge path. The present disclosure improves the anti-interference ability and data transmission efficiency of the data transmission circuit.

First claim

The invention claimed is:

1. A data transmission circuit, comprising:
a sense amplifier circuit, wherein the sense amplifier circuit generates an amplified signal based on a signal at a first terminal and a signal at a second terminal;
a first sub-discharge path, electrically connected to the first terminal and a first data line, wherein the first sub-discharge path discharges from the first terminal to a discharge terminal based on a signal of the first data line in a read state;
a second sub-discharge path, electrically connected to the second terminal and configured to receive a discharge adjustment signal, wherein the second sub-discharge path discharges from the second terminal to the discharge terminal based on the discharge adjustment signal in the reading state; and
a discharge adjustment unit, wherein the discharge adjustment unit is not electrically connected to the first sub-discharge path but is electrically connected to the second sub-discharge path and configured to receive a control signal, wherein the discharge adjustment unit generates the discharge adjustment signal based on the control signal to adjust a discharge capacity of the second sub-discharge path;
wherein the control signal comprises a first sub-control signal, wherein the discharge adjustment signal comprises a first sub-discharge adjustment signal; wherein the discharge adjustment unit comprises:
a first sub-discharge adjustment circuit, electrically connected to a first terminal of the second sub-discharge path and configured to receive the first sub-control signal, wherein the first sub-discharge adjustment circuit provides the first sub-discharge adjustment signal to the second sub-discharge path based on the first sub-control signal;
wherein the control signal further comprises a second sub-control signal, the discharge adjustment signal further comprises a second sub-discharge adjustment signal; and wherein the discharge adjustment unit further comprises:
a second sub-discharge adjustment circuit, electrically connected to a second terminal of the second sub-discharge path and configured to receive the second sub-control signal, wherein the second sub-discharge adjustment circuit is configured to provide the second sub-discharge adjustment signal to the second sub-discharge path based on the second sub-control signal;
wherein the first sub-discharge adjustment circuit comprises:
a first transistor, wherein a source of the first transistor is electrically connected to a first voltage, and a gate is configured to receive the first sub-control signal;
a second transistor, wherein a source of the second transistor is electrically connected to a second voltage, a drain is electrically connected to the drain of the first transistor and the first terminal of the second sub-discharge path, and a gate is configured to receive the first sub-control signal; and
a first energy storage unit, electrically connected to both the drain of the first transistor and the drain of the second transistor.

2. The data transmission circuit of claim 1 , wherein the second sub-discharge adjustment circuit comprises:
a third transistor, wherein a source of the third transistor is electrically connected to the first voltage, and a gate of the third transistor is configured to receive the second sub-control signal;
a fourth transistor, wherein a source of the fourth transistor is electrically connected to the second voltage, a drain of the fourth transistor is electrically connected to the drain of the third transistor and the second terminal of the second sub-discharge path, and a gate of the fourth transistor is configured to receive the second sub-control signal; and
a second energy storage unit, wherein the second energy storage unit is electrically connected to the drain of the third transistor and the drain of the fourth transistor.

3. The data transmission circuit according to claim 1 , wherein the first energy storage unit comprises:
a first MOS transistor, wherein a source and a drain of the first MOS transistor are both electrically connected to a first voltage node, and a gate of the first MOS transistor is electrically connected to the drain of the first transistor, the drain of the second transistor and the first terminal of the second sub-discharge path; and/or
a capacitor, wherein a first terminal of the capacitor is electrically connected to the first voltage node, a second terminal of the capacitor is electrically connected to the drain of the first transistor, the drain of the second transistor, and the first terminal of the second sub-discharge path.

4. The data transmission circuit of claim 3 , wherein:
the first voltage node is grounded; or
the first voltage node is electrically connected to a first controllable voltage output unit;
wherein the first controllable voltage output unit provides a controllable voltage to the first voltage node based on the first sub-control signal.

5. The data transmission circuit according to claim 4 , wherein the first controllable voltage output unit comprises:
a first NOR gate, comprising an output terminal electrically connected to the first voltage node, a first input terminal configured to receive the first sub-control signal, and a second input terminal electrically connected to discharging terminals of the first sub-discharge path and the second sub-discharge paths.

6. The data transmission circuit according to claim 1 , wherein the sense amplifier circuit comprises:
an amplifying unit, electrically connected to both the discharge terminals of the first sub-discharge path and the second sub-discharge path; and
an output circuit, electrically connected to an equalization signal, a first terminal of the sense amplifier circuit, a second terminal of the sense amplifier circuit, a second data line and a second complementary data line;
wherein the sense amplifier circuit provides the amplified signal to the second data line and the second complementary data line, based on the equalization signal, a signal provided by the first sub-discharge path and a signal provided by the second sub-discharge path, wherein the second data line and the second complementary data line transmit mutually inverse data.

7. The data transmission circuit according to claim 6 , wherein the sense amplifier circuit further comprises:
a precharge module, electrically connected to a third terminal of the sense amplifier circuit and a fourth terminal of the sense amplifier circuit, wherein the precharge module performs precharging.

8. The data transmission circuit of claim 7 , wherein the output circuit further comprises:
a first sub-output circuit, wherein the first sub-output circuit is electrically connected to the second terminal of the sense amplifier circuit, the second data line and the second complementary data line, for outputting the amplified signal; and
a second sub-output circuit, wherein the second sub-output circuit is electrically connected to the first terminal of the sense amplifier circuit, the second data line and the second complementary data line, for outputting the amplified signal and matching an output load of the amplifying unit.

9. The data transmission circuit of claim 8 , wherein the output circuit further comprises:
a first switch unit, wherein the first terminal of the sense amplifier circuit is electrically connected to the equalization signal via the first switch unit; and
a second switch unit, wherein the second terminal of the sense amplifier circuit is electrically connected to the equalization signal via the second switch unit.

10. The data transmission circuit according to claim 1 , wherein, further comprising:
a discharge terminal control circuit, wherein the discha

Assignees

• Changxin Memory Tech Inc

Inventors

• Wu Xianjun
• Shang Weibing
• Shi Xiaoqing

Classifications

• G11C7/1096

  Write circuits, e.g. I/O line write drivers · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C7/1048

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title