Memory control circuit providing die-level read retry table, memory package, and storage device

Patent metadata

Field	Value
Publication number	US-12283307-B2
Application number	US-202218063007-A
Country	US
Kind code	B2
Filing date	Dec 7, 2022
Priority date	Jul 25, 2022
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

A storage device includes a memory including a plurality of word lines, a plurality of bit lines and a plurality of memory cells, and a controller configured to control the memory and perform a read retry operation for the memory using a read retry table. The memory includes a special block that stores a read retry table in which a plurality of read retry values are set for each of a plurality of first conditions and each of a plurality of second conditions corresponding to each of the plurality of first conditions.

First claim

What is claimed is:

1. A storage device comprising:
a memory including a plurality of word lines, a plurality of bit lines and a plurality of memory cells, and including a special block that stores a read retry table in which a plurality of read retry values are set for each of a plurality of first conditions and each of a plurality of second conditions corresponding to each of the plurality of first conditions; and
a controller configured to control the memory and perform a read retry operation for the memory using the read retry table,
wherein the read retry table is optimized for each condition with respect to the memory by obtaining samples of read voltages for each of the plurality of first conditions and each of the plurality of second conditions and clustering the samples through machine learning.

2. The storage device according to claim 1 , wherein the plurality of read retry values are set for each of a plurality of third conditions corresponding to each of the plurality of second conditions.

3. The storage device according to claim 2 , wherein the first condition is numbers of cycles, the second condition is retention periods, and the third condition is numbers of read disturbances.

4. The storage device according to claim 1 , wherein the plurality of read retry values are set for a word line group including at least two word lines from among the plurality of word lines.

5. The storage device according to claim 4 , wherein at least two word line groups correspond to each of the plurality of first conditions and each of the plurality of second conditions.

6. The storage device according to claim 1 , wherein the plurality of read retry values are set for a memory block group including at least two memory cells from among the plurality of memory cells.

7. The storage device according to claim 1 , wherein the controller calculates read retry values for a first condition, and for a second condition not set in the read retry table, using the plurality of first conditions and the plurality of second conditions previously set in the read retry table.

8. The storage device according to claim 1 , wherein the controller generates optimal read retry values in each of the plurality of first conditions and each of the plurality of second conditions for the memory.

9. The storage device according to claim 1 , wherein the controller updates the read retry table stored in the special block.

10. A memory package comprising:
a first memory including a first special block storing a first read retry table in which a plurality of first read retry values are set for each of a plurality of first conditions and each of a plurality of second conditions corresponding to each of the plurality of first conditions, wherein the first read retry table is optimized for each condition with respect to the first memory by obtaining samples of read voltages for each of the plurality of first conditions and each of the plurality of second conditions and clustering the samples through machine learning; and
a second memory including a second special block storing a second read retry table in which a plurality of second read retry values are set for each of the plurality of first conditions and each of the plurality of second conditions, wherein the second read retry table is optimized for each condition with respect to the second memory by obtaining samples of read voltages for each of the plurality of first conditions and each of the plurality of second conditions and clustering the samples through machine learning.

11. The memory package according to claim 10 , wherein the plurality of second read retry values are set independently of the plurality of first read retry values.

12. The memory package according to claim 10 , wherein at least some of the plurality of second read retry values are different from at least some of the plurality of first read retry values.

13. The memory package according to claim 10 , further comprising:
a controller configured to control the first memory and the second memory, perform a read retry operation for the first memory using the first read retry table, and perform a read retry operation for the second memory using the second read retry table.

14. The memory package according to claim 13 , wherein the controller updates at least one of the first read retry table or the second read retry table.

15. The memory package according to claim 10 , wherein the plurality of first read retry values are optimal values which are set for the first memory, and the plurality of second read retry values are optimal values which are set for the second memory.

16. A memory control circuit comprising:
a read retry generator configured to generate a read retry table in which a plurality of read retry values are set for each of a plurality of first conditions and each of a plurality of second conditions with respect to at least one memory, wherein the read retry table is optimized for each condition with respect to the at least one memory by obtaining samples of read voltages for each of the plurality of first conditions and each of the plurality of second conditions and clustering the samples through machine learning; and
a read retry outputter configured to store the read retry table in a special block of the at least one memory.

17. The memory control circuit according to claim 16 , wherein the plurality of first conditions are the numbers of cycles, the plurality of second conditions are retention periods, and at least two second conditions correspond to each of the plurality of first conditions.

18. The memory control circuit according to claim 16 , wherein
the at least one memory includes a first memory and a second memory,
the read retry generator generates a first read retry table for the first memory and generates a second read retry table for the second memory, and
the first read retry table is different from the second read retry table.

Assignees

• Sk Hynix Inc

Inventors

• Son Jae Yong
• Kim Nam Kyeong
• Cho Hoon
• Kwon Hyuk Min
• Kim Dae Sung
• Kim Jang Seob
• Yun Sang Ho

Classifications

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C11/4078

  Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52) · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C16/32

  Timing circuits · CPC title