Display substrate and display panel

Patent metadata

Field	Value
Publication number	US-12283244-B2
Application number	US-202418740752-A
Country	US
Kind code	B2
Filing date	Jun 12, 2024
Priority date	Sep 10, 2020
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

A display substrate, including a base substrate, and a driving circuit layer and light emitting elements formed on the base substrate, and in a same pixel circuit, an active general layer includes a first column-wise active portion including active layers of a data writing transistor and a first light emission control transistor, and a first active connection portion, an orthographic projection of the first active connection portion on the base substrate at least partially overlapping an orthographic projection of a corresponding power supply line on the base substrate, a dimension of the first active connection portion in a row direction of the pixel units less than a dimension of the active layer of the data writing transistor in the row direction, and a dimension of the active layer of the first light emission control transistor in the row direction. A display panel is further provided.

First claim

The invention claimed is:

1. A display substrate, comprising a base substrate, and a driving circuit layer and a plurality of light emitting elements formed on the base substrate, the display substrate being divided into a plurality of pixel units arranged in a plurality of rows and a plurality of columns, the driving circuit layer comprising a plurality of pixel circuits corresponding to the plurality of pixel units, the pixel circuits being configured to drive the light emitting elements to emit light,
the driving circuit layer comprises an active pattern layer and a source-drain pattern layer along a thickness direction of the display substrate, the source-drain pattern layer is arranged on a side of the active pattern layer away from the base substrate, the source-drain pattern layer comprises a plurality of power supply lines and a plurality of data lines, length directions of the power supply lines and the data lines are the same as a column direction of the pixel units, each column of pixel units correspond to the power supply line and the data line;
the pixel circuit comprises a plurality of thin film transistors, and in the same pixel unit, active layers of the thin film transistors of the pixel circuit is formed into an active general layer with an integrated structure in a single piece, and the active pattern layer comprises a plurality of active general layers;
the thin film transistors of the pixel circuit comprise a data writing transistor and a first light emission control transistor, and in the same pixel circuit, the active general layer comprises a first column-wise active portion comprising the active layer of the data writing transistor, the active layer of the first light emission control transistor, and a first active connection portion connected between the active layer of the data writing transistor and the active layer of the first light emission control transistor,
wherein the thin film transistors of the pixel circuit comprise a first reset transistor configured to reset an anode of the light emitting element;
in the thickness direction of the display substrate, the driving circuit layer comprises a first gate pattern layer and a second gate pattern layer which are arranged in a stacked mode, the second gate pattern layer is located on a side, away from the active pattern layer, of the first gate pattern layer;
the second gate pattern layer comprises an initial signal line, the source-drain pattern layer further comprises an initialization connector, one end of the initialization connector is electrically coupled to the initial signal line through a through hole, another end of the initialization connector is coupled to a portion, corresponding to the first reset transistor, of the active general layer through a through hole; and
wherein there is an overlap between an orthographic projection of the through hole at one end of the initialization connector on a reference line extending in the row direction and an orthographic projection of the through hole at another end of the initialization connector on the reference line.

2. The display substrate of claim 1 , wherein the first gate pattern layer and the second gate pattern layer both are located between the active pattern layer and the source-drain pattern layer.

3. The display substrate of claim 1 , wherein a length direction of the initialization connector is consistent with the column direction of the pixel units, and a distance between centerlines, in the column direction, of through holes at two ends of the initialization connector is less than or equal to a preset distance.

4. The display substrate of claim 3 , wherein the preset distance is between 0.1 μm and 0.5 μm.

5. The display substrate of claim 1 , wherein an orthographic projection of the first active connection portion on the base substrate at least partially overlaps an orthographic projection of the corresponding power supply line on the base substrate.

6. The display substrate of claim 1 , wherein a dimension of the first active connection portion in a row direction of the pixel units is less than a dimension of the active layer of the data writing transistor in the row direction of the pixel units, and the dimension of the first active connection portion in the row direction of the pixel units is less than a dimension of the active layer of the first light emission control transistor along the row direction of the pixel units.

7. The display substrate of claim 1 , wherein the power supply line and the data line corresponding to the same column of pixel units are arranged on a same side of the column of pixel units.

8. The display substrate of claim 1 , wherein the first gate pattern layer comprises a reset signal line.

9. The display substrate of claim 8 , wherein the active general layer comprises a second column-wise active portion, the second column-wise active portion comprises the active layer of the first reset transistor, and an orthographic projection of the initialization connector on the base substrate partially overlaps with an orthographic projection of the second column-wise active portion on the base substrate.

10. The display substrate of claim 9 , wherein the pixel circuit comprises a second reset transistor and a driving transistor, the second reset transistor is configured to reset a gate of the driving transistor;
the active general layer further comprises a third column-wise active portion and a fourth column-wise active portion, the third column-wise active portion is coupled to the second column-wise active portion through a second active connection portion, the fourth column-wise active portion is coupled to the third column-wise active portion through a third active connection portion, and one end of the third column-wise active portion is coupled to the second active connection portion, another end of the third column-wise active portion is coupled to the third active connection portion, and the corresponding reset signal line sequentially passes through the second column-wise active portion, the third column-wise active portion, and the fourth column-wise active portion, a part of the second column-wise active portion passed by the reset signal line is formed as the active layer of the first reset transistor, parts of the third column-wise active portion and the fourth column-wise active portion passed by the reset signal line are formed as the active layer of the second reset transistor;
the through hole corresponding to the another end of the initialization connector is positioned in the second active connection portion.

11. The display substrate of claim 1 , wherein the first gate pattern layer further comprises a plurality of gate lines, each row of the pixel units corresponds to the gate line, the pixel circuit comprises a compensation transistor,
the gate line comprises a transverse gate line portion and a longitudinal gate line portion, each pixel unit corresponds to one longitudinal gate line portion, and the active layer of the compensation transistor comprises a portion of the active general layer passing through the transverse gate line portion and a portion of the active general layer passing through the longitudinal gate line portion.

12. The display substrate of claim 1 , wherein each four adjacent pixel units form a pixel unit group, and the four pixel units are respectively one red pixel unit, two green pixel units and one blue pixel unit.

13. The display substrate of claim 12 , wherein in the same pixel unit group, the four pixel units are arranged in the row direction in the following order:
the blue pixel unit, the green pixel unit, the red pixel unit and the green pixel uni

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Li Huijun
• Shang Tinghua
• Wang Siyu
• Huang Yan
• Yang Lulu
• Liu Tingliang
• Yang Huijuan
• Jiang Xiaofeng

Classifications

• H10K59/126 Primary

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• G09G2320/0209

  Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display · CPC title

• G09G2300/0809

  Several active elements per pixel in active matrix panels · CPC title