Retrieving diagnostic information from a PCI express endpoint

Patent metadata

Field	Value
Publication number	US-12282380-B2
Application number	US-202117926078-A
Country	US
Kind code	B2
Filing date	May 18, 2021
Priority date	May 18, 2020
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

The present disclosure relates to systems, methods, and computer-readable media for facilitating efficient retrieval of diagnostic information from a computing endpoint that experiences a failure condition. For example, systems described herein may detect or otherwise identify a failure condition associating with the computing endpoint operating in an erroneous or unpredictable matter. Systems described herein may involve carving out a portion of memory on the computing endpoint that is accessible to a host system (e.g., a CPU). Systems described herein may further provide a discoverable resource that enables a host system to identify and collect the diagnostic data in response to identifying a failure condition in an efficient manner and without requiring that the computing endpoint be capable of responding to data requests.

First claim

What is claimed is:

1. A method, comprising:
storing, at a host system, an identifier of a memory register associated with a computing endpoint, the memory register including mapping information indicating a memory location of diagnostic data maintained on the computing endpoint;
identifying a failure condition of the computing endpoint associated with collecting the diagnostic data from the computing endpoint;
in response to identifying the failure condition of the computing endpoint, accessing the mapping information associated with the identifier of the memory register; and
collecting the diagnostic data from the computing endpoint based on the mapping information included within the memory register on the computing endpoint, wherein collecting the diagnostic data comprises causing a root complex on the host system to retrieve the diagnostic data from the indicated memory location without providing a request to the computing endpoint for the diagnostic data.

2. The method of claim 1 , wherein the computing endpoint comprises a peripheral component interconnect express (PCIe) endpoint.

3. The method of claim 1 , wherein the host system and the computing endpoint are coupled via a peripheral component interconnect express (PCIe) communication link, and wherein collecting the diagnostic data from the computing endpoint includes receiving the diagnostic data via the PCIe communication link.

4. The method of claim 1 , wherein identifying the failure condition comprises detecting that the computing endpoint is non-responsive to one or more communications from the host system.

5. The method of claim 1 , wherein identifying the failure condition comprises receiving an interrupt signal from the computing endpoint indicating availability of a crash dump on the computing endpoint at the memory location corresponding to the mapping information.

6. The method of claim 1 , further comprising configuring an endpoint-specific driver on the host system, the endpoint-specific driver including instructions associated with:
identifying the failure condition; and
collecting the diagnostic data in response to identifying the failure condition.

7. The method of claim 1 , wherein the memory register further includes address information for the host system, and wherein the mapping information indicates a range of memory addresses on the computing endpoint that are exposed to the host system based on a source address of the host system matching address information within the memory register.

8. The method of claim 1 , wherein the computing endpoint comprises one or more of a graphics processing unit (GPU), a storage controller, a network adapter, or a processing accelerator.

9. The method of claim 1 , further comprising storing, at the host system, a plurality of identifiers of a plurality of memory registers on a plurality of computing endpoints, the plurality of memory registers including mapping information indicating memory locations of diagnostic data maintained on respective computing endpoints of the plurality of computing endpoints.

10. A system, comprising:
one or more processors;
memory in electronic communication with the one or more processors; and
instructions stored in the memory, the instructions being executable by the one or more processors to cause a host system to:
store an identifier of a memory register associated with a computing endpoint, the memory register including mapping information indicating a memory location of diagnostic data maintained on the computing endpoint;
identify a failure condition of the computing endpoint associated with collecting the diagnostic data from the computing endpoint;
in response to identifying the failure condition of the computing endpoint, access the mapping information associated with the identifier of the memory register; and
collect the diagnostic data from the computing endpoint based on the mapping information included within the memory register on the computing endpoint, wherein collecting the diagnostic data comprises causing a root complex on the host system to retrieve the diagnostic data from the indicated memory location without providing a request to the computing endpoint for the diagnostic data.

11. The system of claim 10 , wherein the computing endpoint comprises a peripheral component interconnect express (PCIe) endpoint, wherein the host system and the PCIe endpoint are coupled via a PCIe communication link, and wherein collecting the diagnostic data from the computing endpoint includes receiving the diagnostic data via the PCIe communication link.

12. The system of claim 10 , wherein identifying the failure condition comprises one or more of:
detecting that the computing endpoint is non-responsive to one or more communications from the host system; or
receiving an interrupt signal from the computing endpoint indicating availability of a crash dump on the computing endpoint at the memory location corresponding to the mapping information.

13. The system of claim 10 , wherein the memory register further includes address information for the host system, and wherein the mapping information indicates a range of memory addresses on the computing endpoint that are exposed to the host system based on a source address of the host system matching address information within the memory register.

14. A non-transitory computer readable medium storing instructions thereon that, when executed by one or more processors on a host system, cause the host system to:
store an identifier of a memory register associated with a computing endpoint, the memory register including mapping information indicating a memory location of diagnostic data maintained on the computing endpoint;
identify a failure condition of the computing endpoint associated with collecting the diagnostic data from the computing endpoint;
in response to identifying the failure condition of the computing endpoint, access the mapping information associated with the identifier of the memory register; and
collect the diagnostic data from the computing endpoint based on the mapping information included within the memory register on the computing endpoint,
wherein collecting the diagnostic data comprises causing a root complex on the host system to retrieve the diagnostic data from the indicated memory location without providing a request to the computing endpoint for the diagnostic data.

15. The non-transitory computer readable medium of claim 14 , wherein the computing endpoint comprises a peripheral component interconnect express (PCIe) endpoint, wherein the host system and the PCIe endpoint are coupled via a PCIe communication link, and wherein collecting the diagnostic data from the computing endpoint includes receiving the diagnostic data via the PCIe communication link.

16. The non-transitory computer readable medium of claim 14 , wherein identifying the failure condition comprises one or more of:
detecting that the computing endpoint is non-responsive to one or more communications from the host system; or
receiving an interrupt signal from the computing endpoint indicating availability of a crash dump on the computing endpoint at the memory location corresponding to the mapping information.

17. The non-transitory computer readable medium of claim 14 , wherein the memory register further includes address information for the host system, and wherein the mapping information indicates a range of memory addresses on the computing endpoint that are exposed to the host system based on a source address of the host system matching address information within the memo

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Jain Vishal
• Mapes Teague Curtiss
• Ross Jonathan Kent

Classifications

• G06F11/0778 Primary

  Dumping, i.e. gathering error/state information after a fault for later diagnosis · CPC title

• G06F11/0745

  in an input/output transactions management context (input/output processing in general G06F13/00) · CPC title

• G06F11/0772 Primary

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title