Electronic device for performing clock management by using clock counters allocated at different power domains and associated method

Patent metadata

Field	Value
Publication number	US-12282352-B2
Application number	US-202318139939-A
Country	US
Kind code	B2
Filing date	Apr 26, 2023
Priority date	Apr 26, 2023
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

An electronic device includes a first circuit block and a second circuit block. The first circuit block is allocated in a first power domain, and includes a first clock counter and an updating circuit. The first clock counter is arranged to generate a first counter value according to a first reference clock. The updating circuit is arranged to receive a second counter value, and update the first counter value according to the second counter value. The second circuit block is allocated in a second power domain, and includes a second clock counter arranged to generate the second counter value according to a second reference clock. The first power domain and the second power domain are controlled independently.

First claim

What is claimed is:

1. An electronic device comprising:
a first circuit block, allocated in a first power domain, wherein the first circuit block comprises:
a first clock counter, arranged to generate a first counter value according to a first reference clock; and
an updating circuit, arranged to receive a second counter value, and update the first counter value according to the second counter value; and

a second circuit block, allocated in a second power domain, wherein the second circuit block comprises:
a second clock counter, arranged to generate the second counter value according to a second reference clock;

wherein the first power domain and the second power domain are controlled independently, and the updating circuit comprises:
a unit-time counter, arranged to generate a unit-time counter value by counting a unit time of the second reference clock according to the first reference clock, wherein a frequency of the first reference clock is higher than a frequency of the second reference clock; and
a calculation circuit, arranged to update the first counter value according to the second counter value and the unit-time counter value.

2. The electronic device of claim 1 , wherein the second power domain remains switched on during a period in which the first power domain is switched off.

3. The electronic device of claim 2 , wherein the second circuit block further comprises:
a volatile memory, arranged to store a backup of the first counter value generated by the first clock counter before a start time of the period; and
the updating circuit is further arranged to restore the first counter value by reading the backup from the volatile memory after an end time of the period.

4. The electronic device of claim 2 , wherein the first circuit block further comprises:
a non-volatile memory, arranged to store a backup of the first counter value generated by the first clock counter before a start time of the period; and
the updating circuit is further arranged to restore the first counter value by reading the backup from the non-volatile memory after an end time of the period.

5. The electronic device of claim 1 , wherein the electronic device is a wireless communication device.

6. The electronic device of claim 5 , wherein the wireless communication device is a Bluetooth device.

7. A clock management method comprising:
using a first clock counter allocated in a first power domain for generating a first counter value according to a first reference clock;
using a second clock counter allocated in a second power domain for generating a second counter value according to a second reference clock;
using an updating circuit allocated in the first power domain for receiving the second counter value and updating the first counter value according to the second counter value; and
controlling the first power domain and the second power domain independently;

wherein using the updating circuit allocated in the first power domain for receiving the second counter value and updating the first counter value according to the second counter value comprises:
generating a unit-time counter value by counting a unit time of the second reference clock according to the first reference clock, wherein a frequency of the first reference clock is higher than a frequency of the second reference clock; and
updating the first counter value according to the second counter value and the unit-time counter value.

8. The clock management method of claim 7 , wherein controlling the first power domain and the second power domain independently comprises:
keeping the second power domain switched on during a period in which the first power domain is switched off.

9. The clock management method of claim 8 , further comprising:
before a start time of the period, storing a backup of the first counter value in a volatile memory allocated in the second power domain;

wherein using the updating circuit allocated in the first power domain for receiving the second counter value and updating the first counter value according to the second counter value comprises:
after an end time of the period, restoring the first counter value by reading the backup from the volatile memory.

10. The clock management method of claim 8 , further comprising:
before a start time of the period, storing a backup of the first counter value in a non-volatile memory allocated in the first power domain;

wherein using the updating circuit allocated in the first power domain for receiving the second counter value and updating the first counter value according to the second counter value comprises:
after an end time of the period, restoring the first counter value by reading the backup from the non-volatile memory.

11. The clock management method of claim 7 , wherein the clock management method is employed by a wireless communication device.

12. The clock management method of claim 11 , wherein the wireless communication device is a Bluetooth device.

Assignees

• Airoha Tech Corp

Inventors

• Huang I-Ping
• Chung Ching-An

Classifications

• G06F1/14

  Time supervision arrangements, e.g. real time clock · CPC title

• G06M1/27

  for representing the result of count in the form of electric signals, e.g. by sensing markings on the counter drum · CPC title

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title