Array substrate and display device

Patent metadata

Field	Value
Publication number	US-12282233-B2
Application number	US-202218547390-A
Country	US
Kind code	B2
Filing date	Nov 29, 2022
Priority date	Nov 29, 2022
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

An array substrate includes: a base substrate, a light shielding layer on a first surface of the base substrate, and a plurality of pixel units and a first common electrode bus on a second surface of the base substrate. The base substrate includes a display region, first and second peripheral regions. Orthographic projections of the pixel units on the base substrate are arranged in an array in the display region. At least part of an orthographic projection of the light shielding layer and at least part of an orthographic projection of the first common electrode bus on the base substrate are in the second peripheral region, and the first common electrode bus is electrically connected to the common electrode included in at least one pixel unit. A distribution density of the first common electrode bus in the first peripheral region is smaller than that in the second peripheral region.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate comprising a first surface and a second surface opposite to the first surface, wherein the base substrate comprises a display region and a peripheral region surrounding the display region, the peripheral region comprises a first peripheral region surrounding the display region and a second peripheral region surrounding the first peripheral region;
a plurality of pixel units located on the second surface of the base substrate, wherein orthographic projections of the plurality of pixel units on the base substrate are located in the display region and distributed in an array, and at least one of the plurality of pixel units comprises a common electrode;
a light shielding layer located on the first surface of the base substrate, wherein an orthographic projection of the light shielding layer on the base substrate is located in the peripheral region, and at least part of the orthographic projection of the light shielding layer on the base substrate is located in the second peripheral region; and
a first common electrode bus located on the second surface of the base substrate, wherein an orthographic projection of the first common electrode bus on the base substrate is located at least partially in the second peripheral region, and the first common electrode bus is electrically connected to the common electrode,
wherein a material of the first common electrode bus comprises a metal material, and a distribution density of the first common electrode bus in the first peripheral region is less than a distribution density of the first common electrode bus in the second peripheral region;
wherein an orthographic projection of a boundary of the first common electrode bus close to the display region on the base substrate is located at a junction of the first peripheral region and the second peripheral region; and
wherein the orthographic projection of the boundary of the first common electrode bus close to the display region on the base substrate is located in the orthographic projection of the light shielding layer on the base substrate.

2. The array substrate according to claim 1 , wherein the first common electrode bus comprises a first part located in the first peripheral region and a second part located in the second peripheral region, the second part comprises a block-shaped metal portion, and
wherein the first part comprises a strip-shaped metal portion.

3. The array substrate according to claim 2 , wherein the first part of the first common electrode bus located in the first peripheral region comprises a plurality of strip-shaped metal portions and at least one strip-shaped slit, and the plurality of strip-shaped metal portions and the at least one strip-shaped slit are alternately arranged in a direction from an edge of the base substrate to the display region of the base substrate.

4. The array substrate according to claim 3 , wherein the strip-shaped slit has a first width in a first direction, the strip-shaped metal portion has a second width in the first direction, and the first direction is substantially perpendicular to an extension direction of the strip-shaped slit or an extension direction of the strip-shaped metal portion; and
wherein a value of dividing the first width by a sum of the first width and the second width is greater than or equal to 0.5.

5. The array substrate according to claim 3 , wherein a ratio of a length of the at least one strip-shaped slit in an extension direction of the at least one strip-shaped slit to a width of the at least one strip-shaped slit in a direction perpendicular to the extension direction of the at least one strip-shaped slit is greater than or equal to 10.

6. The array substrate according to claim 1 , wherein the base substrate comprises a first side, a second side, a third side and a fourth side, the first side and the second side are arranged opposite to each other, and the third side and the fourth side are arranged opposite to each other;
wherein the array substrate further comprises a data signal line and a scanning signal line arranged on the second surface of the base substrate, the scanning signal line extends from the first side toward the second side, and the data signal line extends from the third side toward the fourth side; and
wherein at least two columns of dummy pixel units are arranged in the first peripheral region on at least one of the first side and the second side.

7. The array substrate according to claim 6 , wherein at least one row of dummy pixel units is arranged in the first peripheral region on at least one of the third side and the fourth side.

8. The array substrate according to claim 6 , wherein on at least one of the first side and the second side, the first part of the first common electrode bus located in the first peripheral region comprises a plurality of first strip-shaped metal portions extending in a second direction, and a plurality of second strip-shaped metal portions extending in a third direction intersecting with the second direction.

9. The array substrate according to claim 8 , wherein the first direction intersects with the third direction.

10. The array substrate according to claim 1 , wherein the base substrate comprises a first side, a second side, a third side and a fourth side, the first side and the second side are arranged opposite to each other, and the third side and the fourth side are arranged opposite to each other;
wherein the array substrate further comprises a data signal line and a scanning signal line arranged on the second surface of the base substrate, the scanning signal line extends from the first side toward the second side, and the data signal line extends from the third side toward the fourth side; and
wherein at least one column of dummy pixel units is arranged between a first part and the display region in the first peripheral region on at least one of the first side and the second side.

11. The array substrate according to claim 10 , wherein the array substrate further comprises a second common electrode bus located on the second surface of the base substrate, an orthographic projection of the second common electrode bus on the base substrate is located in the first peripheral region and the second peripheral region, and the second common electrode bus is electrically connected to the first common electrode bus.

12. The array substrate according to claim 11 , wherein on at least one of the first side and the second side, the first part of the first common electrode bus located in the first peripheral region comprises a plurality of first strip-shaped metal portions extending in a second direction, and a plurality of second strip-shaped metal portions extending in a third direction intersecting with the second direction; and
wherein the second common electrode bus comprises at least one second opening located in the first peripheral region, and an orthographic projection of at least one intersecting portion between the plurality of first strip-shaped metal portions and the plurality of second strip-shaped metal portions on the base substrate overlaps at least partially with an orthographic projection of the at least one second opening on the base substrate.

13. The array substrate according to claim 12 , wherein on at least one of the first side and the second side, a part of the scanning signal line located in the peripheral region comprises a first scanning signal sub-portion and a second scanning signal sub-portion, the first scanning signal sub-portion extends in a first direction, and the second scanning signal sub-portion extends in the second direction intersec

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Wang Tingting
• Wang Xu
• Wang Qi
• Yan Yan
• Ma Yu
• Yin Xiaofeng
• Ma Zhiqiang
• Gong Tao
• Ren Haoyan

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/136209 Primary

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

• G02F1/134318 Primary

  having a patterned common electrode · CPC title