Display panel and display device

Patent metadata

Field	Value
Publication number	US-12279459-B2
Application number	US-202318384578-A
Country	US
Kind code	B2
Filing date	Oct 27, 2023
Priority date	Dec 30, 2020
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

A display panel includes a base substrate, a third transistor and a fourth transistor. The third transistor and the fourth transistor are formed on the base substrate. The third transistor includes a sixth gate electrode, a third active layer, a third source electrode, and a third drain electrode. The third active layer includes an oxide semiconductor. The fourth transistor includes an eighth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode. The fourth active layer includes another oxide semiconductor. Along a direction perpendicular to the base substrate, a distance between the sixth gate electrode and the third active layer is D 6 . A channel region of the third transistor defined by the sixth gate electrode is a sixth channel region. A length of the sixth channel region is L 6 . A sixth area S 6 =L 6 ×D 6.

First claim

What is claimed is:

1. A display panel, comprising:
a base substrate;
a third transistor and a fourth transistor;
wherein:
the third transistor and the fourth transistor are formed on the base substrate;
the third transistor includes a sixth gate electrode, a third active layer, a third source electrode, and a third drain electrode;
the third active layer includes an oxide semiconductor;
the fourth transistor includes an eighth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode; and
the fourth active layer includes another oxide semiconductor;
along a direction perpendicular to the base substrate, a distance between the sixth gate electrode and the third active layer is D 6 , a channel region of the third transistor defined by the sixth gate electrode is a sixth channel region, a length of the sixth channel region is L 6 , and a sixth area S 6 =L 6 ×D 6 ; and
along the direction perpendicular to the base substrate, a distance between the eighth gate electrode and the fourth active layer is D 8 , a channel region of the fourth transistor defined by the eighth gate electrode is an eighth channel region, a length of the eighth channel region is L 8 , and an eighth area S 8 =L 8 ×D 8 ; and
a pixel circuit and a drive circuit providing a drive signal for the pixel circuit, wherein the third transistor is a drive transistor of the pixel circuit, the fourth transistor is a switch transistor of the pixel circuit, and S 6 >S 8 , wherein:
the third transistor further includes a fifth gate electrode, and along the direction perpendicular to the base substrate, a distance between the fifth gate electrode and the third active layer is D 5 , a channel region of the third transistor defined by the fifth gate electrode is a fifth channel region, a length of the fifth channel region is L 5 , and a fifth area S 5 =L 5 ×D 5 ,
the fourth transistor further includes a seventh gate electrode, and along the direction perpendicular to the base substrate, a distance between the seventh gate electrode and the fourth active layer is D 7 , a channel region of the fourth transistor defined by the seventh gate electrode is a seventh channel region, a length of the seventh channel region is L 7 , and a seventh area S 7 =L 7 ×D 7 , and
(S 6 −S 5 )> (S 8 −S 7 ),
wherein S 8 ≠S 7 .

2. The display panel according to claim 1 , wherein:
D 5 <D 6 and/or S 5 <S 6 .

3. The display panel according to claim 2 , wherein:
D 7 <D 8 and/or S 7 <S 8 .

4. The display panel according to claim 3 , wherein:
the drive circuit includes a second transistor; and the second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; and the second active layer includes another oxide semiconductor; and
a length of a channel region of the second transistor is L 2 ; along the direction perpendicular to the base substrate, a distance between the second gate electrode and the second active layer is D 2 ; and a second area S 2 =L 2 ×D 2 , wherein S 2 <S 5 .

5. The display panel according to claim 4 , wherein:
the second transistor further includes a fourth gate electrode; and along the direction perpendicular to the base substrate, a distance between the fourth gate electrode and the second active layer is D 4 ;
a channel region of the second transistor defined by the second gate electrode is a second channel region, and a length of the second channel region is L 2 ;
a channel region of the second transistor defined by the fourth gate electrode is a fourth channel region, and a length of the fourth channel region is L 4 , and a fourth area S 4 =L 4 ×D 4 ; and
D 2 <D 4 , and/or S 2 <S 4 .

6. The display panel according to claim 5 , wherein:
S 6 >S 4 .

7. The display panel according to claim 5 , wherein:
(S 4 −S 2 )<(S 6 −S 5 ).

8. The display panel according to claim 5 , wherein:
(S 6 −S 5 )+(S 4 −S 2 )>2 (S 8 −S 7 ).

9. The display panel according to claim 1 , further comprising a first transistor, wherein:
the first transistor is included in one of the pixel circuit and the drive circuit; and
the first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; the first active layer includes silicon; a length of a channel region of the first transistor is L 1 ; along the direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D 1 ; and a first area S 1 =L 1 ×D 1 , wherein S 1 <S 5 .

10. The display panel according to claim 5 , wherein:
the pixel circuit further includes a first capacitor, configured to store a data voltage transmitted to a gate electrode of the third transistor, wherein the sixth gate electrode is multiplexed as a plate of the first capacitor.

11. The display panel according to claim 10 , wherein:
the drive circuit further includes a second capacitor;
the fourth gate electrode is multiplexed as a plate of the second capacitor; and
a capacitance value of the first capacitor is greater than a capacitance value of the second capacitor.

12. The display panel according to claim 1 , wherein:
the display panel is a foldable display panel which includes a bending axis extending along a first direction; and
an angle between a length direction of a channel region of a second transistor and the first direction is greater than 45 degrees, and an angle between a length direction of a channel region of a first transistor and the first direction is less than 45 degrees.

13. The display panel according to claim 12 , wherein:
the length direction of the channel region of the second transistor is perpendicular to the first direction; and
the length direction of the channel region of the first transistor is in parallel with the first direction.

14. A display panel, comprising:
a base substrate;
a third transistor and a fourth transistor;
wherein:
the third transistor and the fourth transistor are formed on the base substrate; the third transistor includes a sixth gate electrode, a third active layer, a third source electrode, and a third drain electrode;
the third active layer includes an oxide semiconductor; the fourth transistor includes an eighth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode; and
the fourth active layer includes another oxide semiconductor;
along a direction perpendicular to the base substrate, a distance between the sixth gate electrode and the third active layer is D 6 , a channel region of the third transistor defined by the sixth gate electrode is a sixth channel region, a length of the sixth channel region is L 6 , and a sixth area S 6 =L 6 ×D 6 ;
along the direction perpendicular to the base substrate, a distance between the eighth gate electrode and the fourth active layer is D 8 , a channel region of the fourth transistor defined by the eighth gate electrode is an eighth channel region, a length of the eighth channel region is L 8 , and an eighth area S 8 =L 8 ×D 8 , wherein S 6 >S 8 ;
the third transistor further includes a fifth gate electrode, and along the direction perpendicular to the base substrate, a distance between the fifth gate electrode and the third active layer is D 5 , a channel region of the third transistor defined by the fifth gate electrode is a fifth channel region, a length of the fifth channel region is L 5 , and a fifth area S 5 =L 5 ×D 5 ;
the fourth transistor further includes a seventh gate electrode, and along the direction perpendicular to the base substrate, a distance between the seventh

Assignees

• Xiamen Tianma Micro Electronics Co Ltd

Inventors

• Lai Qingjun
• Zhu Yihua
• Yuan Yong
• An Ping
• Cao Zhaokeng

Classifications

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D86/431

  having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• G09G2300/0814

  used for selection purposes, e.g. logical AND for partial update · CPC title