LDMOS transistor and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12279442-B2
Application number	US-202117508251-A
Country	US
Kind code	B2
Filing date	Oct 22, 2021
Priority date	Oct 23, 2020
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

A LDMOS transistor and manufacturing method includes: forming an epitaxial layer on a substrate of a first doping type; forming a gate structure on an upper surface of the epitaxial layer; forming a source region of a second doping type in the epitaxial layer, the second doping type is opposite to the first doping type; forming a patterned first insulating layer on the upper surface of the epitaxial layer and the gate structure, and at least exposes part of the source region; forming a first conductive channel by using a sidewall as a mask, the first conductive channel extends from the source region to an upper surface of the substrate so as to connect the source region with the substrate; and forming a drain region of the second doping type in the epitaxial layer.

First claim

What is claimed is:

1. An LDMOS transistor comprising:
an epitaxial layer on a substrate of a first doping type;
a gate structure on an upper surface of the epitaxial layer;
a source region of a second doping type in the epitaxial layer, wherein the second doping type is opposite to the first doping type;
a patterned first insulating layer on the upper surface of the epitaxial layer and the gate structure, wherein the patterned first insulating layer at least comprises a sidewall covering a side surface of the gate structure close to the source region;
a first conductive channel extending from the source region to an upper surface of the substrate, wherein the source region is connected with the substrate through the first conductive channel;
a shield conductor layer covering the first conductive channel and the patterned first insulating layer; and
a drain region in the epitaxial layer,
wherein the gate structure comprises:
a gate dielectric layer on the upper surface of the substrate, a gate conductor on the gate dielectric layer, a silicide layer on the gate conductor, a third insulating layer on the silicide layer, and a first barrier layer on the third insulating layer, at least dimensions of the gate dielectric layer, the gate conductor, the silicide layer and the third insulating layer correspond, and

wherein the shield conductor layer is sequentially in contact with an upper surface of the first conductive channel, the sidewall, an upper surface of the third insulating layer, a side surface of the first barrier layer, an upper surface of the patterned first insulating layer.

2. The LDMOS transistor according to claim 1 , wherein the first conductive channel is formed self-aligned by use of the sidewall as a mask.

3. The LDMOS transistor according to claim 1 , wherein the patterned first insulating layer exposes at least part of an upper surface of the gate structure.

4. The LDMOS transistor according to claim 1 , wherein the first conductive channel is in contact with prat part of a side surface of the sidewall.

5. The LDMOS transistor according to claim 1 , wherein the shield conductor layer exposes the patterned first insulating layer close to the drain region.

6. The LDMOS transistor according to claim 1 , wherein further comprising:
a body contact region of the first doping type in the substrate, the first conductive channel connecting the body contact region and the source region.

7. The LDMOS transistor according to claim 1 , wherein further comprising: a body region of the first second doping type in a first region of the epitaxial layer extending from the upper surface of the epitaxial layer to an interior of the epitaxial layer, wherein the source region is located in the body region, and the body region at least partially extends to the epitaxial layer below the gate structure.

8. The LDMOS transistor according to claim 1 , wherein further comprising: a drift region of the second doping type in a second region of the epitaxial layer extending from the upper surface of the epitaxial layer to an interior of the epitaxial layer, wherein the drain region is located in the drift region.

9. The LDMOS transistor according to claim 1 , wherein further comprising:
a second insulating layer on the shielding conductor layer and the patterned first insulating layer;
a drain electrode on an upper surface of the second insulating layer; and
a second conductive channel connecting the drain region and the drain electrode, the second conductive channel extending from the second insulating layer to the drain region.

10. The LDMOS transistor according to claim 1 , wherein the gate dielectric layer, the gate conductor, the silicide layer and the third insulating layer is of a same width, and a width of the first barrier layer is less than a width of the third insulating layer.

11. The LDMOS transistor according to claim 1 , wherein part of an upper surface of the third insulating layer close to the source region is exposed by the first barrier layer.

12. The LDMOS transistor according to claim 1 , wherein the first barrier layer is a nitride.

13. The LDMOS transistor according to claim 1 , wherein further comprising: a source electrode located on a lower surface of the substrate.

Assignees

• Hangzhou Silicon Magic Semiconductor Tech Co Ltd

Inventors

• Wang Jiakun
• Wu Bing

Classifications

• H10W10/051

  of isolation region based on field-effect · CPC title

• H10W10/50

  Isolation regions based on field-effect · CPC title

• H10D64/111 Primary

  Field plates · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D30/65

  Lateral DMOS [LDMOS] FETs · CPC title