Conductive substrate and carrier plate wiring structure with filtering function, and manufacturing method of same

Patent metadata

Field	Value
Publication number	US-12279377-B2
Application number	US-202217955855-A
Country	US
Kind code	B2
Filing date	Sep 29, 2022
Priority date	Mar 25, 2022
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

A manufacturing method for a conductive substrate with a filtering function includes preparing a core layer and forming first and second conductive holes in the core layer, forming a sacrificial copper layer on the first conductive hole and on the core layer, forming a metal layer on the second conductive hole, forming a metal post in the first conductive hole, forming a lower insulating layer on the core layer, forming a lower insulative post in the second conductive hole, forming a magnet wrapping around the metal post to obtain a first conductive post, forming an upper insulating layer on the core layer, forming an upper insulative post in the second conductive hole to obtain a second conductive post, removing the upper insulating layer, the lower insulating layer, and the remaining sacrificial copper post layer, followed by flattening.

First claim

What is claimed is:

1. A method for manufacturing a conductive substrate with a filtering function, the comprising:
(a) preparing a core layer, and forming at least one first conductive hole and at least one second conductive hole respectively penetrating through the core layer in a height direction in the core layer;
(b) forming a sacrificial copper layer on an inner wall of the at least one first conductive hole and on a surface of the core layer, respectively, and forming a metal layer on the inner wall of the at least one second conductive hole;
(c) forming the metal post in the at least one first conductive hole;
(d) etching a part of the sacrificial copper layer on a lower surface of the core layer to expose a bottom end of the metal post, forming a lower insulating layer covering the bottom end of the metal post on the lower surface of the core layer, and forming a lower insulative post in the at least one second conductive hole;
(e) etching a part of the sacrificial copper layer on an upper surface of the core layer and the sacrificial copper layer on the inner wall of the at least one first conductive hole, and forming a magnet wrapping around the metal post in an axial direction between the inner wall of the at least one first conductive hole and the metal post to obtain a first conductive post layer;
(f) continuing to etch a part of the sacrificial copper layer on the upper surface of the core layer, forming an upper insulating layer covering a top end of the metal post on the upper surface of the core layer, and forming an upper insulative post in the at least one second conductive hole, the upper insulative post and the lower insulative post together forming an insulating column filling the second conductive hole to obtain a second conductive post layer; and
(g) removing remaining sacrificial copper post layers on the upper surface and lower surface of the upper insulating layer, the lower insulating layer, and the core layer, and grinding ends of the first conductive post layer and the second conductive post layer respectively such that the end of the first conductive post layer and the end of the second conductive post layer are respectively flush with the core layer to obtain a conductive substrate with a filtering function.

2. The method of claim 1 , wherein step (d) comprises:
(d1) respectively applying a first photoresist layer and a second photoresist layer on the upper surface and lower surface of the core layer, and exposing and developing the second photoresist layer to form a second feature pattern;
(d2) etching exposed partial sacrificial copper layer on the lower surface of the core layer in the second feature pattern, and exposing the bottom end of the metal post;
(d3) removing the first photoresist layer and the second photoresist layer; and
(d4) laminating an insulating material on the lower surface of the core layer to form a lower insulating layer covering the bottom end of the metal post, and forming a lower insulative post in the at least one second conductive hole.

3. The method of claim 1 , wherein step (e) comprises:
(e1) applying a third photoresist layer on the upper surface of the core layer, and exposing and developing the third photoresist layer to form a third feature pattern exposing a top end of the at least one first conductive hole;
(e2) etching a sacrificial copper layer on the inner wall of the at least one first conductive hole in the third feature pattern;
(e3) removing the third photoresist layer;
(e4) forming a magnet wrapping around the metal post in the axial direction between the inner wall of the at least one first conductive hole and the metal post; and
(e5) flattening the magnet and the metal post to obtain a first conductive post layer.

4. The method of claim 3 , wherein step (e4) comprises forming a magnet wrapping around the metal post in the axial direction between the inner wall of the at least one first conductive hole and the metal post by means of silk screening.

5. The method of claim 1 , wherein step (f) comprises:
(f1) respectively applying a fourth photoresist layer on the upper surface and lower surface of the core layer, and exposing and developing the fourth photoresist layer to form a fourth feature pattern;
(f2) etching the exposed partial sacrificial copper layer on the upper surface of the core layer in the fourth feature pattern;
(f3) removing the fourth photoresist layer; and
(f4) laminating an insulating material on the upper surface of the core layer, forming an upper insulating layer covering the top end of the metal post, and forming an upper insulative post in the at least one second conductive hole, the upper insulative post and the lower insulative post together forming an insulative post filling the second conductive hole, and the metal layer and the insulative post together forming a second conductive post layer.

6. A method for manufacturing a carrier plate wiring structure, the method comprising:
(a) preparing the conductive substrate with a filtering function manufactured by the method of claim 1 ; and
(b) respectively forming a first circuit layer and a second circuit layer on an upper surface and a lower surface of the conductive substrate, wherein the first circuit layer and the second circuit layer are conductively connected through the first conductive post layer or the second conductive post layer.

7. The method of claim 6 , further comprising:
(c), following step (b), respectively forming a first adding layer and a second adding layer on the first circuit layer and the second circuit layer, respectively forming a first copper post layer and a second copper post layer in the first adding layer and the second adding layer, and respectively forming a third circuit layer and a fourth circuit layer on the surfaces of the first adding layer and the second adding layer respectively, wherein the first circuit layer and the third circuit layer are conductively connected through the first copper post layer, and the second circuit layer and the fourth circuit layer are conductively connected through the second copper post layer; and
(j) forming a third adding layer and a fourth adding layer on the third circuit layer and the fourth circuit layer respectively, forming a third copper post layer and a fourth copper post layer in the third adding layer and the fourth adding layer respectively, and forming a fifth circuit layer and a sixth circuit layer on the surfaces of the third adding layer and the fourth adding layer respectively, wherein the third circuit layer and the fifth circuit layer are conductively connected through the third copper post layer, and the fourth circuit layer and the sixth circuit layer are conductively connected through the fourth copper post layer.

Assignees

• Zhuhai Access Semiconductor Co Ltd

Inventors

• Chen Xianming
• Xu Xiaowei
• Huang Gao
• Huang Benxia

Classifications

• H10W70/635

  Through-vias · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W40/258

  Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title

• H10W70/095

  of vias therein · CPC title