Video processor, video processing method, display control system, and electronic device

Patent metadata

Field	Value
Publication number	US-12279069-B2
Application number	US-202018266579-A
Country	US
Kind code	B2
Filing date	Dec 21, 2020
Priority date	Dec 21, 2020
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

Provided is a video processor. The video processor includes: a receiving module, configured to receive source video display data and parse the source video display data as valid video display data; a pre-processing module, configured to generate valid video display data in a predetermined video format; an image quality processing module, configured to adjust image quality parameters to output a first video screen; a post-processing module, configured to extract video parameters, generate a blended screen, and blend the blended screen on the first video screen; and a video output module, configured to perform data format conversion on valid video display data of the first video screen and valid video display data of the blended screen to encapsulate as output video display data, and output the output video display data to an external display to blend the blended screen on the first video screen.

First claim

The invention claimed is:

1. A video processor, comprising:
a receiving module, configured to receive source video display data adopting different communication protocols over at least one input interface and parse the source video display data adopting the different communication protocols as valid video display data;
a pre-processing module, connected to the receiving module, and configured to generate valid video display data in a predetermined video format by pre-processing a video format of the valid video display data;
an image quality processing module, connected to the pre-processing module, and configured to adjust image quality parameters in the valid video display data in the predetermined video format to output a first video screen;
a post-processing module, connected to the pre-processing module and the image quality processing module, and configured to extract video parameters in the valid video display data, generate a blended screen based on the video parameters, and blend the blended screen on the first video screen; and
a video output module, connected to the post-processing module, and configured to perform data format conversion on valid video display data of the first video screen and valid video display data of the blended screen to encapsulate as output video display data, and output the output video display data to an external display over a video output interface to blend the blended screen on the first video screen for display.

2. The video processor according to claim 1 , wherein the input interface comprises:
a first input interface module, configured to receive source video display data adopting an 12G-serial digital interface (SDI) communication protocol, a 6G-SDI communication protocol, a 3G-SDI communication protocol, or a high definition-serial digital interface (HD-SDI) communication protocol;
a second input interface, configured to receive source video display data adopting a high definition multimedia interface (HDMI) 2.0 communication protocol;
a third input interface, configured to receive source video display data adopting a display port (DP) 1.2 communication protocol; and
a fourth input interface, configured to receive source video display data of an on-screen display (OSD) menu screen.

3. The video processor according to claim 1 , wherein the image quality parameters comprise hue, chromaticity, contrast, brightness, color temperature, gamut, a gamma correction parameter, and a color space conversion parameter.

4. The video processor according to claim 1 , further comprising: an audio transmitting module and an audio processing module, wherein the audio transmitting module is configured to receive audio data over the input interface, parse the audio data as valid audio data in a predetermined data format, and transmit to the audio processing module, such that the audio processing module processes the valid audio data and outputs to an external playback module.

5. The video processor according to claim 1 , wherein the input interface further comprises an external controller interface, wherein the external controller interface is configured to be connected to an external controller, such that the external controller upgrades a system of the video processor and monitors the video processor over the external controller interface.

6. The video processor according to claim 2 , wherein the receiving module comprises:
a first receiving unit, connected to the first input interface module, and configured to parse the source video display data adopting the 12G-SDI communication protocol, the 6G-SDI communication protocol, the 3G-SDI communication protocol, or the HD-SDI communication protocol as first valid video display data;
a second receiving unit, connected to the second input interface, and configured to parse the source video display data adopting the HDMI 2.0 communication protocol as second valid video display data;
a third receiving unit, connected to the third input interface, and configured to parse the source video display data adopting the DP 1.2 communication protocol as third valid video display data; and
a fourth receiving unit, connected to the fourth input interface, and configured to parse the source video display data of the OSD menu screen as fourth valid video display data;
wherein data formats of the first valid video display data, the second valid video display data, the third valid video display data, and the fourth valid video display data are the same.

7. The video processor according to claim 2 , wherein the pre-processing module comprises a synchronization unit and a first cache controller, wherein the synchronization unit is configured to synchronize valid video display data from the different input interfaces by storing the valid video display data from different input interfaces to an external cache for the first cache controller to read the valid video display data from the different input interfaces from the external cache based on a synchronization clock.

8. The video processor according to claim 6 , wherein
the first input interface module comprises at least one set of SDI input interfaces, wherein each of the at least one set of SDI input interfaces comprises four SDI input interfaces configured to receive four different channels of source video display data;
the first receiving unit comprises at least one receiving sub-unit connected to the at least one set of SDI input interfaces, wherein each of the at least one receiving sub-unit is configured to convert the four different channels of source video display data to four different channels of valid video display data; and
the pre-processing module further comprises a quad display connector, wherein the quad display connector is connected to the receiving sub-unit, and is configured to convert the four different channels of valid video display data received by the receiving sub-unit to valid video display data in a predetermined video format, and perform image pasting on four channels of valid video display data in the predetermined video format based on a predetermined rule.

9. The video processor according to claim 7 , wherein the pre-processing module further comprises a definition converting unit, configured to perform definition conversion on the synchronized valid video display data, such that a definition of the synchronized valid video display data reaches a target definition.

10. The video processor according to claim 9 , wherein the definition converting unit performs the definition conversion on the synchronized valid video display data in a definition multiplication conversion manner, wherein pixel supplementation is performed in a case that a definition of the multiplication converted valid video display data is less than the target definition, such that a definition of a display screen reaches the target definition.

11. The video processor according to claim 9 , wherein the pre-processing module further comprises a scan mode converting unit, configured to determine an input scan mode of the valid video display data, and uniformly convert the scan mode of the valid video display data to a progressive scan based on a result of the determination.

12. The video processor according to claim 11 , wherein in the case that the scan mode of the valid video display data is an interlaced scan:
valid video display data corresponding to odd rows of an odd frame and valid video display data corresponding to even rows of an adjacent even frame are interspersed and combined, such that the interlaced scan is converted to the progressive scan; or
the valid video display data corresponding to the odd rows of the odd frame is kept unchanged, black pixels are

Assignees

• Boe Technology Group Co Ltd

Inventors

• Geng Lihua
• Wu Congrui
• Ma Xitong
• Duan Ran
• Xia Youxiang

Classifications

• H04N21/4331

  Caching operations, e.g. of an advertisement for later insertion during playback · CPC title

• H04N21/4302

  Content synchronisation processes, e.g. decoder synchronisation · CPC title

• H04N7/0127

  by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter · CPC title

• H04N5/265 Primary

  Mixing · CPC title

• G09G2310/0224

  Details of interlacing · CPC title