System and methods for sigma-delta modulation

Patent metadata

Field	Value
Publication number	US-12278652-B2
Application number	US-202318129991-A
Country	US
Kind code	B2
Filing date	Apr 3, 2023
Priority date	Apr 3, 2023
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

A device and method for sigma-delta modulation may include an input signal and a plurality of integrators. The output of the integrators and a data input may be input to an adder, the sum output to be input to a quantizer to generate a quantized output signal. A reset input to the first integrator may be asserted during a first sample of the quantized output signal to reduce the signal discontinuity at the input of the first integrator, which improves the stability of the sigma-delta modulator.

First claim

The invention claimed is:

1. A device comprising:
an input adder with a positive input coupled to an input signal and a negative input coupled to a feedback signal;
a first integrator with a data input coupled to an output of the input adder and a reset input coupled to an output of a reset circuit;
a plurality of downstream integrators, each downstream integrator comprising a data input and a reset input, wherein the data inputs of the plurality of downstream integrators are connected in series, wherein the input of the first of the plurality of downstream integrators is coupled to an output of the first integrator, and wherein the plurality of downstream integrators comprises a last integrator and wherein the reset input of the plurality of downstream integrators are respectively coupled to an output of the reset circuit;
an output adder with inputs coupled, respectively, to the output of the first integrator, to the output of one or more of the plurality of downstream integrators, and to an output of a feedforward path, the feedforward path comprising a gain stage coupled between the input signal and the output adder;
a quantizer with an input coupled to the output of the output adder, the quantizer to generate a quantized output signal;
a digital-to-analog converter with an input coupled to the quantized output signal and an output comprising the feedback signal;
wherein the reset circuit to generate a first reset signal to be coupled to the reset input of the first integrator and one or more second reset signals to be coupled to the reset inputs of, respectively, the plurality of downstream integrators, the first reset signal and the second reset signal to be de-asserted at different times, and
the first reset signal to be asserted during a first sample of the quantized output signal and to be de-asserted after the first sample of the quantized output signal.

2. The device as claimed in claim 1 , the second reset signal to be de-asserted prior to the first sample of the quantized output signal.

3. The device as claimed in claim 1 , the input adder comprising a first gain stage coupled to the positive input and a second gain stage coupled to the negative input.

4. A method comprising:
subtracting a feedback signal from an input signal at an input adder to generate a difference signal;
integrating the difference signal in a plurality of integrator stages, the plurality of integrator stages comprising a first integrator and one or more downstream integrators, wherein the integrator stages are connected in series and wherein a de-assertion of a reset signal to the first integrator is prior to the de-assertion of a reset signal to the downstream integrators;
quantizing, at a quantizer, a sum of, respectively, the output of at least one of the plurality of integrator stages and the input signal, an output of the quantizer comprising a quantized output signal,
converting the quantized output signal into the feedback signal in a digital-to-analog converter, and wherein
the reset signal to the first integrator to be asserted during a first sample of the quantized output signal and to be de-asserted after the first sample of the quantized output signal.

5. The method as claimed in claim 4 , the reset signal to the downstream integrators be de-asserted prior to the first sample of the quantized output signal.

Assignees

• Microchip Tech Inc

Inventors

• Quiquempoix Vincent

Classifications

• H03M3/376

  Prevention or reduction of switching transients, e.g. glitches · CPC title

• H03M3/364

  by resetting one or more loop filter stages · CPC title

• H03M3/352 Primary

  of deviations from the desired transfer characteristic · CPC title

• H03M3/452 Primary

  with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input · CPC title