Semiconductor device

Patent metadata

Field	Value
Publication number	US-12278263-B2
Application number	US-202318505684-A
Country	US
Kind code	B2
Filing date	Nov 9, 2023
Priority date	Mar 11, 2021
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

A semiconductor device includes a semiconductor part, a first electrode and control electrodes at the front side of the semiconductor part. The semiconductor part includes first to fourth layers, first and third layers being of a first conductivity type, second and fourth layers being of a second conductivity type. The control electrodes are provided in a plurality of trenches, respectively. The control electrodes include a first control electrode, and a second control electrode next to the first control electrode. The second layer is provided between the first layer and the first electrode. The third and fourth layers are provided between the second layer and the first electrode. The semiconductor part further includes a first region partially provided between the first and second layers. The first region is provided between the first and third layers, the first region including a material having a lower thermal conductivity than the first layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor part including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a fourth semiconductor layer of the second conductivity type, a plurality of trenches provided at a front side of the semiconductor part;
a first electrode provided at the front side of the semiconductor part; and
a plurality of control electrodes provided in the plurality of trenches, respectively, the plurality of control electrodes each being electrically insulated from the semiconductor part via an insulating film, the plurality of control electrodes including a first control electrode, and a second control electrode next to the first control electrode,
the second semiconductor layer being provided between the first semiconductor layer and the first electrode, the second semiconductor layer being provided between the first and second control electrodes, the second semiconductor layer facing the first and second control electrodes via the insulating film,
the third and fourth semiconductor layers being provided between the second semiconductor layer and the first electrode, the third and fourth semiconductor layers being electrically connected to the first electrode and arranged along a front surface of the second semiconductor layer facing the first electrode,
the semiconductor part further including a first region partially provided between the first semiconductor layer and the second semiconductor layer, the first region being provided between the first semiconductor layer and the third semiconductor layer, the first region including a material having a lower thermal conductivity than the first semiconductor layer,
the third semiconductor layer being apart from the fourth semiconductor layer,
the second semiconductor layer including a portion provided between the third semiconductor layer and the fourth semiconductor layer.

2. The device according to claim 1 , wherein
the plurality of control electrodes includes a planar control portion, the planar control portion being provided on a front surface of the semiconductor part facing the first electrode, and
the planar control portion links the first and second control electrodes and faces the portion of the second semiconductor layer via the insulating film.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Suwa Takeshi
• Matsudai Tomoko
• Iwakaji Yoko
• Itokazu Hiroko

Classifications

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D12/481

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title