Interface circuit and memory controller

Patent metadata

Field	Value
Publication number	US-12277288-B2
Application number	US-202318213907-A
Country	US
Kind code	B2
Filing date	Jun 26, 2023
Priority date	Jan 18, 2023
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results and includes a compensation control mechanism selection circuit which selects a corresponding compensation control mechanism according to the monitored results and set it as a currently-operating compensation control mechanism to control the hardware circuits to operate in compliance with the currently-operating compensation control mechanism.

First claim

What is claimed is:

1. An interface circuit, comprising:
a signal processing circuit, configured to process a reception signal received from a host device and a transmission signal to be transmitted to the host device, wherein the signal processing circuit comprises:
a plurality of signal processing devices; and
a monitor and calibration module, comprising:
a plurality of monitor circuits, configured to monitor at least one of an amplitude, a frequency and a jitter in at least one of the reception signal and the transmission signal to generate a monitored result corresponding to the at least one of the amplitude, the frequency and the jitter in the at least one of the reception signal and the transmission signal and to monitor at least one of a power supplying voltage and a ground voltage to generate a monitored result corresponding to the at least one of the power supplying voltage and the ground voltage in a monitor and calibration procedure;
a plurality of calibration circuits, coupled to the signal processing devices and respectively configured to perform a calibration operation on at least one of the signal processing devices in the monitor and calibration procedure to adjust a characteristic value of the at least one of the signal processing devices; and
a compensation control mechanism operation logic, coupled to the monitor circuits and the calibration circuits and configured to collect the monitored results from the monitor circuits and sequentially generate a calibration control signal corresponding to each calibration circuit based on the monitored results to respectively control the corresponding calibration circuit to perform the calibration operation on the at least one of the signal processing devices in response to the calibration control signal,

wherein the compensation control mechanism operation logic comprises a plurality of hardware circuits, and the hardware circuits comprise:
a compensation control mechanism selection circuit, comprising a plurality of compensation control mechanism selection logics and configured to select a compensation control mechanism corresponding to the monitored results based on the monitored results and set the compensation control mechanism as a currently-operating compensation control mechanism to control at least one of the hardware circuits to operate in compliance with the currently-operating compensation control mechanism.

2. The interface circuit of claim 1 , wherein the interface circuit is configured inside of a memory controller and the signal processing circuit is a Serializer-Deserializer (SerDes).

3. The interface circuit of claim 1 , wherein the hardware circuits further comprise:
a calibration handle interface, coupled to the calibration circuits and configured to receive and decode a calibration command and generate the calibration control signal according to a decoding result of the calibration command, and transmit the calibration control signal to at least one of the calibration circuits.

4. The interface circuit of claim 3 , wherein the hardware circuits further comprise:
a monitor handle interface, coupled to the monitor circuits and configured to receive and decode a monitor command to generate a monitor control signal according to a decoding result of the monitor command, and provide the monitor control signal to at least one of the monitor circuits.

5. The interface circuit of claim 4 , wherein the hardware circuits further comprise:
a monitor management logic, coupled to the monitor handle interface and configured to manage the monitor circuits through the monitor handle interface, buffer the monitored results collected from the monitor circuits and generate the monitor command according to a monitor selection control signal to activate the at least one of the monitor circuits corresponding to the monitor command to perform a monitor operation.

6. The interface circuit of claim 5 , wherein the hardware circuits further comprise:
a monitor detection and selection logic, coupled to the monitor management logic and configured to determine an activation sequence of the monitor circuits in the monitor and calibration procedure according to the currently-operating compensation control mechanism and correspondingly generate the monitor selection control signal.

7. The interface circuit of claim 6 , wherein the hardware circuits further comprise:
a calibration management logic, coupled to the calibration handle interface and configured to manage the calibration circuits through the calibration handle interface, buffer a plurality of calibration results collected from the calibration circuits and generate the calibration command according to a calibration selection control signal to activate the at least one of the calibration circuits corresponding to the calibration command to perform the calibration operation.

8. The interface circuit of claim 7 , wherein the hardware circuits comprise:
a calibration trigger and selection logic, coupled to the calibration management logic and configured to determine an activation sequence of the calibration circuits in the monitor and calibration procedure according to the currently-operating compensation control mechanism, and correspondingly generate the calibration selection control signal.

9. A memory controller, coupled to a memory device to control access operations of the memory device, comprising:
a host interface, configured to communicate with a host device and comprising a signal processing circuit to process a reception signal received from the host device and a transmission signal to be transmitted to the host device, wherein the signal processing circuit comprises:
a plurality of signal processing devices; and
a monitor and calibration module, comprising:
a plurality of monitor circuits, configured to monitor at least one of an amplitude, a frequency and a jitter in at least one of the reception signal and the transmission signal to generate a monitored result corresponding to the at least one of the amplitude, the frequency and the jitter in the at least one of the reception signal and the transmission signal and to monitor at least one of a power supplying voltage and a ground voltage to generate a monitored result corresponding to the at least one of the power supplying voltage and the ground voltage in a monitor and calibration procedure;
a plurality of calibration circuits, coupled to the signal processing devices and respectively configured to perform a calibration operation on at least one of the signal processing devices in the monitor and calibration procedure to adjust a characteristic value of the at least one of the signal processing devices; and

a compensation control mechanism operation logic, coupled to the monitor circuits and the calibration circuits and configured to collect the monitored results from the monitor circuits and sequentially generate a calibration control signal corresponding to each calibration circuit based on the monitored results to respectively control the corresponding calibration circuit to perform the calibration operation on the at least one of the signal processing devices in response to the calibration control signal,
wherein the compensation control mechanism operation logic comprises a plurality of hardware circuits, and the hardware circuits comprise:
a compensation control mechanism selection circuit, comprising a plurality of compensation control mechanism selection logics and configured to select a compensation control mechanism corresponding to the monitored results based on the monitored results and set the compensation control mechanism as a currently-operating compensation control mechanism to control at least one of the hardware circuits to operate in c

Assignees

• Silicon Motion Inc

Inventors

• Shih Fu-Jen

Classifications

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G06F13/1673 Primary

  using buffers · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• H04L1/205

  jitter monitoring · CPC title

• H03K19/017509

  Interface arrangements · CPC title