Memory system and operation method thereof and power management module

Patent metadata

Field	Value
Publication number	US-12277018-B2
Application number	US-202318203596-A
Country	US
Kind code	B2
Filing date	May 30, 2023
Priority date	Mar 1, 2023
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

Implementations of the present disclosure disclose a memory system and an operation method thereof. The memory system comprises at least one memory device and a memory controller coupled with the at least one memory device. The memory controller is configured to: in respond to an instruction of a host coupled with the memory system, control the memory system to enter a first activation mode and a transition mode sequentially. The transition mode includes an idle mode and a first sleep mode. A power of the memory system in the first sleep mode is less than a power of the memory system in the idle mode. The power of the memory system in the idle mode is less than a power of the memory system in the first activation mode.

First claim

What is claimed is:

1. A memory system, comprising:
at least one memory device; and
a memory controller coupled with the at least one memory device and configured to:
in respond to an instruction of a host coupled with the memory system, control the memory system to enter a first activation mode and a transition mode sequentially, wherein:
the transition mode includes an idle mode and a first sleep mode,
a power of the memory system in the first sleep mode is less than a power of the memory system in the idle mode, and
the power of the memory system in the idle mode is less than a power of the memory system in the first activation mode.

2. The memory system of claim 1 , wherein the memory controller is further configured to:
control the memory system to enter a second activation mode and a second sleep mode sequentially after being in the transition mode,
wherein a power of the memory system in the second sleep mode is less than a power of the memory system in the second activation mode.

3. The memory system of claim 1 , wherein:
a ratio between a duration of the memory system in the idle mode and a duration of the memory system in the first sleep mode is determined based on historical data of the memory system switching from the idle mode to the first activation mode.

4. The memory system of claim 1 , wherein:
a duration of the memory system in the first sleep mode is longer than a duration of the memory system in the idle mode.

5. The memory system of claim 4 , wherein:
a ratio between the duration of the memory system in the idle mode and the duration of the memory system in the first sleep mode is 1:9.

6. The memory system of claim 2 , wherein:
the second sleep mode includes a Normal Sleep mode and a Deep Sleep mode;
the first sleep mode includes the Normal Sleep mode;
a power of the memory system in the Deep Sleep mode is less than a power of the memory system in the Normal Sleep mode; and
in a process of controlling the memory system to enter the second sleep mode, the memory controller is further configured to:
control the memory system to enter the Normal Sleep mode,
maintain the memory system in the Normal Sleep mode for a period of time, and
control the memory system to enter the Deep Sleep mode.

7. The memory system of claim 6 , wherein the memory controller is further configured to:
when the memory system enters the Normal Sleep mode, cut off a power supply of the at least one memory device.

8. The memory system of claim 6 , wherein the memory controller is further configured to:
store current data into the at least one memory device before the memory system entering the Deep Sleep mode.

9. The memory system of claim 6 , wherein the memory controller is further configured to:
when the memory system entering the Deep Sleep mode, cut off a power supply of the at least one memory device, a power supply of an interface between the memory controller and the host, and a power supply of the memory controller.

10. The memory system of claim 1 , wherein the memory system comprises a Universal Flash Storage apparatus.

11. A method of operating a memory system, comprising:
controlling, by a memory controller of the memory system in respond to an instruction of a host coupled with the memory system, the memory system to enter a first activation mode and a transition mode sequentially;
wherein:
the transition mode includes an idle mode and a first sleep mode,
a power of the memory system in the first sleep mode is less than a power of the memory system in the idle mode, and
the power of the memory system in the idle mode is less than a power of the memory system in the first activation mode.

12. The method of claim 11 , further comprising:
controlling, by the memory controller, the memory system to enter a second activation mode and a second sleep mode sequentially after being in the transition mode,
wherein a power of the memory system in the second sleep mode is less than a power of the memory system in the second activation mode.

13. The method of claim 12 , wherein:
controlling the memory system in the first sleep mode includes controlling the memory system in a Normal Sleep mode;
controlling the memory system in the second sleep mode includes:
controlling the memory system to enter the Normal Sleep mode,
maintaining the memory system in the Normal Sleep mode for a period of time, and
controlling the memory system to enter a Deep Sleep mode; and

a power of the memory system in the Deep Sleep mode is less than a power of the memory system in the Normal Sleep mode.

14. The method of claim 13 , further comprising:
cut off, by the memory controller when the memory system enters the Normal Sleep mode, a power supply of the at least one memory device.

15. The method of claim 13 , further comprising:
store, the memory controller before the memory system entering the Deep Sleep mode, current data into the at least one memory device.

16. The method of claim 13 , further comprising:
cut off, by the memory controller when the memory system entering the Deep Sleep mode, a power supply of the at least one memory device, a power supply of an interface between the memory controller and the host, and a power supply of the memory controller.

17. A non-transitory medium containing computer-executable instructions that, when executed by a hardware controller of a first electrical device, cause the hardware controller to perform a power management method for the first electrical device, the method comprising:
controlling, in respond to an instruction of a second electrical device coupled with the first electrical device, the first electrical device to enter a first activation mode and a transition mode sequentially;
wherein:
the transition mode includes an idle mode and a first sleep mode,
a power of the first electrical device in the first sleep mode is less than a power of the first electrical device in the idle mode, and
the power of the first electrical device in the idle mode is less than a power of the first electrical device in the first activation mode.

18. The non-transitory medium of claim 17 , wherein the method further comprises:
controlling the first electrical device to enter a second activation mode and a second sleep mode sequentially after being in the transition mode,
wherein a power of the first electrical device in the second sleep mode is less than a power of the first electrical device in the second activation mode.

19. The non-transitory medium of claim 18 , wherein:
controlling the first electrical device in the first sleep mode includes controlling the first electrical device in a Normal Sleep mode;
controlling the first electrical device in the second sleep mode includes:
controlling the first electrical device to enter the Normal Sleep mode,
maintaining the first electrical device in the Normal Sleep mode for a period of time, and
controlling the first electrical device to enter a Deep Sleep mode; and

a power of the first electrical device in the Deep Sleep mode is less than a power of the first electrical device in the Normal Sleep mode.

20. The non-transitory medium of claim 19 , wherein the method further comprises:
when the first electrical device enters the first sleep mode or the second sleep mode, cutting off a power supply of a functional device in the first electrical device.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Duan Guiyuan
• Chen Meifa

Classifications

• G06F1/3225

  of memory devices · CPC title

• G06F1/3268

  Power saving in hard disk drive · CPC title

• G06F1/3275 Primary

  Power saving in memory, e.g. RAM, cache · CPC title

• G11C5/148 Primary

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title