Low noise phase lock loop (PLL) circuit

Patent metadata

Field	Value
Publication number	US-12273117-B2
Application number	US-202217969251-A
Country	US
Kind code	B2
Filing date	Oct 19, 2022
Priority date	Nov 22, 2021
Publication date	Apr 8, 2025
Grant date	Apr 8, 2025

Abstract

A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.

First claim

What is claimed is:

1. A phase lock loop (PLL) circuit, comprising:
a phase-frequency detector (PFD) circuit configured to determine a difference between a reference clock signal and a feedback clock signal and generate up/down control signals in response to said difference;
a first charge pump operating in response to the up/down control signals to generate a first charge pump current;
a loop filter comprising a capacitor but no resistor that filters the first charge pump signal to generate a control voltage;
a second charge pump operating in response to the up/down control signals to generate a second charge pump current, wherein the second charge pump further receives the control voltage and the second charge pump current is generated dependent on both the control voltage and the up/down control signals;
a voltage controlled oscillator comprising:
a first transconductance circuit controlled by said control voltage to generate a first transconductance current;
a current summing node configured to sum the first transconductance current with the second charge pump current to generate a control current; and
a current controlled oscillator configured to generate an oscillating output signal having a frequency controlled by said control current; and

a divider circuit configured to frequency divide the oscillating output signal to generate the feedback clock signal.

2. The PLL circuit of claim 1 , wherein the second charge pump further includes low pass filter circuitry configured to filter noise from the second charge pump current.

3. The PLL circuit of claim 1 , further comprising a filter circuit configured to filter the second charge pump current before application to the current summing node.

4. The PLL circuit of claim 1 , wherein the first charge pump circuit comprises:
a reference current generator;
current mirroring circuitry configured to generate a sourcing current and a sinking current from the reference current;
a first switching circuit actuated in response to one of said up/down control signals to apply the sourcing current to the first charge pump current; and
a second switching circuit actuated in response to another of said up/down control signals to apply the sinking current to the first charge pump current.

5. The PLL circuit of claim 4 , where said one of said up/down control signals is a down control signal and said another of said up/down control signals is an up signal.

6. The PLL circuit of claim 1 , wherein the second charge pump circuit comprises:
a reference current generator;
current mirroring circuitry configured to generate a sourcing current and a sinking current from the reference current;
a first switching circuit actuated in response to one of said up/down control signals to apply the sourcing current to the second charge pump current; and
a second switching circuit actuated in response to another of said up/down control signals to apply the sinking current to the second charge pump current.

7. The PLL circuit of claim 6 , where said one of said up/down control signals is an up control signal and said another of said up/down control signals is a down signal.

8. The PLL circuit of claim 6 , further comprising low pass filter circuitry on control nodes of the current mirroring circuitry to filter noise from the sourcing and sinking currents.

9. A phase lock loop (PLL) circuit, comprising:
a phase-frequency detector (PFD) circuit configured to determine a difference between a reference clock signal and a feedback clock signal and generate up/down control signals in response to said difference;
a first charge pump operating in response to the up/down control signals to generate a first charge pump current;
a loop filter comprising a capacitor but no resistor that filters the first charge pump signal to generate a control voltage;
a second charge pump operating in response to the up/down control signals to generate a second charge pump current;
a voltage controlled oscillator comprising:
a first transconductance circuit controlled by said control voltage to generate a first transconductance current;
a current summing node configured to sum the first transconductance current with the second charge pump current to generate a control current; and
a current controlled oscillator configured to generate an oscillating output signal having a frequency controlled by said control current; and

a divider circuit configured to frequency divide the oscillating output signal to generate the feedback clock signal; and
wherein the second charge pump circuit comprises:
a voltage regulator circuit configured to generate a first regulated voltage and a second regulated voltage in response to the control voltage;
a second transconductance circuit controlled by said first regulated voltage to generate a second transconductance current;
a third transconductance circuit controlled by said second regulated voltage to generate a third transconductance current;
a current differencing circuit configured to subtract the second transconductance current from the third transconductance current to generate a difference current;
current mirroring circuitry configured to generate a sourcing current and a sinking current from the difference current;
a first switching circuit actuated in response to one of said up/down control signals to apply the sourcing current to the second charge pump current; and
a second switching circuit actuated in response to another of said up/down control signals to apply the sinking current to the second charge pump current.

10. The PLL circuit of claim 9 , where said one of said up/down control signals is an up control signal and said another of said up/down control signals is a down signal.

11. The PLL circuit of claim 9 , further comprising low pass filter circuitry on control nodes of the current mirroring circuitry to filter noise from the sourcing and sinking currents.

12. A phase lock loop (PLL) circuit, comprising:
a phase-frequency detector (PFD) circuit configured to determine a difference between a reference clock signal and a feedback clock signal and generate up/down control signals in response to said difference;
charge pump and loop filter circuitry configured to generate an integral signal component control signal and a proportional signal component control signal in response to said up/down control signals;
wherein said integral signal component control signal and said proportional signal component control signal are separate control signals;
a voltage controlled oscillator configured to generate an oscillating output signal having a frequency controlled by said integral signal component control signal and said proportional signal component control signal; and
a divider circuit configured to frequency divide the oscillating output signal to generate the feedback clock signal; and
wherein said charge pump and loop filter circuitry comprises:
a first charge pump operating in response to the up/down control signals to generate a first charge pump current;
a loop filter that filters the first charge pump signal to generate a control voltage which forms said integral signal component control signal; and
a second charge pump operating in response to the up/down control signals to generate a second charge pump current which forms said proportional signal component control signal, wherein the second charge pump further receives the control voltage and the second charge pump current is generated dependent on both the control voltage and the up/down control signals.

13. The PLL circuit of claim 12 , wherein voltage controlled oscillator comprises:
a first transconducta

Assignees

• St Microelectronics Int Nv

Inventors

• Kumar Anand
• Gupta Prashutosh

Classifications

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title

• H03L7/0893

  the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title