Methods and apparatus to convert analog voltages to delay signals

Patent metadata

Field	Value
Publication number	US-12273104-B2
Application number	US-202318115657-A
Country	US
Kind code	B2
Filing date	Feb 28, 2023
Priority date	Feb 28, 2023
Publication date	Apr 8, 2025
Grant date	Apr 8, 2025

Abstract

An example apparatus includes a first transistor configured to receive an analog voltage signal; a second transistor configured to receive a first control signal, coupled to the first transistor, and coupled to a first terminal; a third transistor configured to receive a second control signal, receive a supply voltage, and coupled to the first terminal; a capacitor coupled to the first terminal and to ground; a fourth transistor configured to receive a third control signal and coupled to the first terminal; a fifth transistor gate configured to receive a bias voltage, coupled to ground, and coupled to the fourth transistor; a sixth transistor coupled to the fourth transistor and to ground; a seventh transistor configured to receive the supply voltage, coupled to the first terminal and to the sixth transistor; and an eighth transistor coupled to the first terminal, to the sixth transistor, and to ground.

First claim

What is claimed is:

1. An apparatus to convert a voltage to a delay signal, the apparatus comprising:
a first transistor having: a first gate configured to receive an analog voltage signal, a first source coupled to ground, and a first drain;
a second transistor having: a second gate configured to receive a first control signal, a second source coupled to the first drain of the first transistor, and a second drain;
a third transistor having: a third gate configured to receive a second control signal, a third source configured to receive a supply voltage, and a third drain coupled to the second drain in the second transistor via a first terminal;
a capacitor having: a positive terminal coupled to the first terminal, and a negative terminal coupled to ground;
a fourth transistor having: a fourth gate configured to receive a third control signal, a fourth source, and a fourth drain coupled to the first terminal;
a fifth transistor having: a fifth gate configured to receive a bias voltage, a fifth source coupled to ground, and a fifth drain coupled to the fourth source of the fourth transistor;
a sixth transistor having: a sixth gate, a sixth source coupled to ground, and a sixth drain coupled to the fourth source of the fourth transistor;
a seventh transistor having: a seventh gate coupled to the first terminal, a seventh source configured to receive the supply voltage, and a seventh drain coupled to the sixth gate of the sixth transistor via second terminal; and
an eighth transistor having: an eighth gate coupled to the first terminal, an eighth source coupled ground, and an eighth drain coupled to the second terminal.

2. The apparatus of claim 1 , wherein the analog voltage is a single-ended signal.

3. The apparatus of claim 1 , wherein:
the second transistor, the third transistor, the capacitor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor collectively form a first set of circuit elements; and
the apparatus further includes a second set of circuit elements, the second set of circuit elements having the same components and same connections as the first set.

4. The apparatus of claim 3 , wherein:
the first set of circuit elements and the second set of circuit elements collectively form a first half circuit; and
the apparatus further includes a second half circuit, the second half circuit having the same components and same connections as the first half circuit.

5. The apparatus of claim 4 , wherein:
the analog voltage signal includes a positive differential signal and a negative differential signal;
the first half circuit is configured to convert the positive differential signal into a first delay signal;
the second half circuit is configured to convert the negative differential signal into a second delay signal; and
a time difference between a rising edge of the first delay signal and a corresponding edge of the second delay signal encodes a state of the analog voltage signal.

6. The apparatus of claim 4 , wherein:
the first set of circuit elements is configured to generate a first pulse in a first delay signal based on a state of the analog voltage signal during a first sample window;
the second set of circuit elements is configured to generate a first pulse in a second delay signal based on the state of the analog voltage signal during the first sample window; and
the first set of circuit elements is further configured to generate a second pulse in the first delay signal based on a state of the analog voltage signal during a second sample window, the second sample window occurring after the first sample window.

7. The apparatus of claim 1 , wherein:
the capacitor is a first capacitor; and
the apparatus further includes:
a second capacitor having: a negative terminal coupled to the gate of the first transistor, and a positive terminal;
a resistor having: a first terminal coupled to the positive terminal of the second capacitor, and a second terminal coupled to an input common mode voltage; and
a ninth transistor having: a ninth gate coupled to the positive terminal of the second capacitor, a ninth source coupled to ground, and a ninth drain coupled to the drain of the first transistor.

8. The apparatus of claim 7 , wherein the second capacitor, the resistor and the ninth transistor are collectively configured to receive high frequencies from the analog voltage signal.

9. The apparatus of claim 7 , wherein:
the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the ninth transistor are NMOS transistors; and
the third transistor, the fourth transistor, the seventh transistor, and the eighth transistor are PMOS transistors.

10. An apparatus to convert an analog voltage to a digital signal, the apparatus comprising:
controller circuitry configured to transmit a first control signal, a second control signal, and a third control signal;
two first transistors both having: a first gate configured to receive an analog voltage signal, a first source coupled to ground, and a first drain;
two second transistors both having: a second gate configured to receive a first control signal, a second source coupled to the first drain of the two first transistors, and a second drain;
two third transistors both having: a third gate configured to receive a second control signal, a third source configured to receive a supply voltage, and a third drain coupled to the second drain in the two second transistors via a first terminal;
two capacitors both having: a positive terminal coupled to the first terminal, and a negative terminal coupled to ground;
two fourth transistors both having: a fourth gate configured to receive a third control signal, a fourth source, and a fourth drain coupled to the first terminal;
two fifth transistors both having: a fifth gate configured to receive a bias voltage, a fifth source coupled to ground, and a fifth drain coupled to the fourth source of the two fourth transistors;
two sixth transistors having: a sixth gate, a sixth source coupled to ground, and a sixth drain coupled to the fourth source of the two fourth transistors;
two seventh transistors having: a seventh gate coupled to the first terminal, a seventh source configured to receive the supply voltage, and a seventh drain coupled to the sixth gate of the two sixth transistors via a second terminal;
two eighth transistors having: an eighth gate coupled to the first terminal, an eighth source coupled ground, and an eighth drain coupled to the second terminal;
and delay to digital circuitry configured to:
obtain a first delay signal from the drain of the two first transistors;
obtain a second delay signal from the drain of the two second transistors; and
determine a value of a digital bit based on the first delay signal and the second delay signal.

11. The apparatus of claim 10 , wherein:
the first delay signal includes a first pulse;
the second delay signal includes a second pulse; and
the delay to digital signal is configured to determine the value of the digital bit based on a difference in time between rising edges of the first pulse and the second pulse.

12. The apparatus of claim 10 , wherein:
a first of the two first transistors, a first of the two second transistors, a first of the two third transistors, a first of the two capacitors, a first of the two fourth transistors, a first of the two fifth transistors, a first of the two sixth transistors, a first of the two seventh transistors, and a first of the two eighth transistors collectively form a first half circuit; and
a second of the two first transistors,

Assignees

• Texas Instruments Inc

Inventors

• Ghosh Sovan
• Pentakota Visvesvaraya Appala

Classifications

• H03K5/01 Primary

  Shaping pulses (discrimination against noise or interference H03K5/125) · CPC title

• H03K2005/00078

  Fixed delay · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/502

  using tapped delay lines · CPC title

• H03K17/6872 Primary

  using complementary field-effect transistors · CPC title