Memory system and operation method of the memory system

Patent metadata

Field	Value
Publication number	US-12271602-B2
Application number	US-202318476145-A
Country	US
Kind code	B2
Filing date	Sep 27, 2023
Priority date	Nov 12, 2021
Publication date	Apr 8, 2025
Grant date	Apr 8, 2025

Abstract

A memory system includes: a storage device for storing data; a system memory in which normal firmware and debugging firmware are stored; a firmware implementer for implementing the normal firmware or the debugging firmware; and a controller for controlling the storage device in a normal mode in which the memory system is driven by the normal firmware. When an error detected in the normal mode is uncorrectable, the controller uploads the debugging firmware stored in the system memory to the firmware implementer to change the normal mode to a debugging mode. The firmware implementer performs a debugging operation on the storage device by implementing the uploaded debugging firmware.

First claim

What is claimed is:

1. A memory system comprising:
a storage device configured to store data;
a system memory in which normal firmware and debugging firmware are stored;
a firmware implementer configured to receive the normal firmware or the debugging firmware from the system memory; and
a controller configured to perform a debugging operation on the storage device by executing the debugging firmware uploaded to the firmware implementer,
wherein, when an error detected in a normal mode is uncorrectable, the debugging firmware stored in the system memory is uploaded to the firmware implementer to change the normal mode to a debugging mode.

2. The memory system of claim 1 , wherein the system memory includes:
a first storage configured to store the normal firmware; and
a second storage configured to store the debugging firmware.

3. The memory system of claim 2 , wherein each of the first and the second storages is configured with at least one of a Read Only Memory (ROM), a Programmable ROM (PROM), an Electrically Programmable ROM (EPROM), an Electrically Erasable and Programmable ROM (EEPROM), or a flash memory.

4. The memory system of claim 1 , wherein the firmware implementer includes:
a processor configured to execute the normal firmware or the debugging firmware, which is uploaded from the system memory; and
a trimming circuit configured to transfer a debugging command, an address, or debugging data according to the debugging firmware, which is uploaded to the processor.

5. The memory system of claim 1 , wherein, when the debugging firmware is uploaded to the firmware implementer, the firmware implementer generates a debugging command, an address, and debugging data.

6. The memory system of claim 5 , wherein the debugging command is a command for performing an operation selected from among a debugging program operation, a debugging read operation, and a debugging erase operation,
the address is a physical address of a memory block included in the storage device, and
the debugging data is data to be temporarily stored in the memory block included in the storage device in the debugging program operation.

7. The memory system of claim 6 , wherein, in the debugging program operation, the debugging firmware programs the debugging data in the memory block included in the storage device.

8. The memory system of claim 7 , wherein the debugging data has a pattern in which data 0 and data 1 are randomly mixed.

9. The memory system of claim 7 , wherein the debugging data has a pattern configured with only one of data 0 and data 1.

10. The memory system of claim 6 , wherein, in the debugging program operation, when a time taken to program the debugging data in the memory block is longer than a debugging reference time or a pulse number of a program voltage used to program the debugging data in the memory block is greater than a debugging reference pulse number, the controller processes the memory block as a bad block by the debugging firmware.

11. The memory system of claim 6 , wherein, in the debugging read operation, the debugging firmware reads debugging data stored in the memory block.

12. The memory system of claim 11 , wherein the controller:
performs the debugging erase operation on a memory block in which an error is detected, when the error is detected in data read from the memory block and when a number of bits of the error is smaller than a debugging reference number having a preset value; and
processes, as a bad block, the memory block in which the error is detected, when the number of bits of the error is equal to or greater than the debugging reference number.

13. The memory system of claim 6 , wherein, when the debugging erase operation is performed, the controller erases data stored in a memory block in which an error is detected among memory blocks included in the storage device by the debugging firmware.

14. The memory system of claim 13 , wherein, when a time taken to perform the debugging erase operation is longer than a debugging reference time or when a pulse number of an erase voltage used for the debugging erase operation is greater than a debugging reference pulse number, the controller processes the memory block in which the error is detected as a bad block by the debugging firmware.

15. The memory system of claim 1 , wherein, when the normal mode is changed to the debugging mode,
the firmware implementer deletes the uploaded normal firmware,
the system memory uploads the debugging firmware to the firmware implementer, and
the controller performs the debugging operation by the uploaded debugging firmware.

16. The memory system of claim 1 , wherein, when the debugging mode is ended,
the firmware implementer deletes the uploaded debugging firmware,
the system memory uploads the normal firmware to the firmware implementer, and
the controller performs a normal operation by the normal firmware.

17. The memory system of claim 16 , wherein, after the debugging mode is changed to the normal mode, the memory system is rebooted.

18. A memory system comprising:
a storage device configured to store data;
a system memory in which first firmware and second firmware are stored;
a firmware implementer configured to receive the first firmware or the second firmware; and
a controller configured to perform a debugging operation on the storage device by the second firmware uploaded to the firmware implementer.

Assignees

• Sk Hynix Inc

Inventors

• Lee Kyu Min
• Jang In Jong

Classifications

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F9/4411

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title

• G06F9/441

  Multiboot arrangements, i.e. selecting an operating system to be loaded · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title