Operation method of memory, memory, memory system, and electronic device

Patent metadata

Field	Value
Publication number	US-12266405-B2
Application number	US-202218089420-A
Country	US
Kind code	B2
Filing date	Dec 27, 2022
Priority date	Nov 18, 2022
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

A memory includes at least a target word line and a first word line group and a second word line group respectively stacked on both sides of the target word line. The first word line group includes first word lines, and the second word line group includes second word lines. A method for operating the memory includes, during a pre-charge operation, applying a first bias voltage signal to the plurality of first word lines, applying a second bias voltage signal to a target word line, and applying a third bias voltage signal to the plurality of second word lines. The method also includes, during a programming operation, applying a program voltage signal to a target word line.

First claim

What is claimed is:

1. A method for programming a memory, the memory comprising at least a target word line and a first word line group and a second word line group stacked on both sides of the target word line, respectively, the first word line group comprising first word lines, the second word line group comprising second word lines, the method comprising:
applying a first bias voltage signal to the first word lines, applying a second bias voltage signal to the target word line, and applying a third bias voltage signal to the second word lines, during a pre-charge operation; and,
applying a program voltage signal to the target word line during a programming operation, wherein the programming operation comprises a first sub-programming operation and a second sub-programming operation, the memory further comprises memory cells, the first word line group comprising a first adjacent word line adjacent to the target word line, the second word line group comprising a second adjacent word line adjacent to the target word line, and the method further comprises:
performing the first sub-programming operation on the memory cells coupled to the first adjacent word line;
performing the pre-charge operation, the first bias voltage signal, the second bias voltage signal, and the third bias voltage signal having a first set of set values;
performing the first sub-programming operation on the memory cells coupled to the target word line;
performing the first sub-programming operation on the memory cells coupled to the second adjacent word line;
performing the pre-charge operation, the first bias voltage signal, the second bias voltage signal, and the third bias voltage signal having a second set of set values; and,
performing the second sub-programming operation on the memory cells coupled to the target word line, the first set of set values being different from the second set of set values.

2. The method according to claim 1 , wherein the first bias voltage signal has a first voltage value, the second bias voltage signal has a second voltage value, the third bias voltage signal has a third voltage value, and the first voltage value, the second voltage value, and the third voltage value are different from one another.

3. The method according to claim 1 , wherein a voltage value of the first bias voltage signal is greater than a voltage value of the second bias voltage signal among the first set of set values, and a voltage value of the third bias voltage signal is greater than a voltage value of the second bias voltage signal among the second set of set values.

4. The method according to claim 1 , wherein the first bias voltage signal, the second bias voltage signal, and the third bias voltage signal are independently controlled during the pre-charge operation.

5. The method according to claim 1 , wherein
the memory cells coupled to each of the second word lines are in an erased state, the first bias voltage signal has a first voltage value, the second bias voltage signal has a second voltage value, and the third bias voltage signal has a third voltage value;
the first voltage value is greater than the second voltage value; and
the second voltage value is equal to the third voltage value.

6. The method according to claim 1 , wherein
the memory cells coupled to each of the second word lines are in an erased state.

7. The method according to claim 1 , wherein
the first word line group is at a side of the target word line close to a bit line; and
the second word line group is at another side of the target word line away from the bit line.

8. A memory, comprising:
a memory array comprising at least a target word line and a first word line group and a second word line group stacked on both sides of the target word line, respectively, the first word line group comprising first word lines, the second word line group comprising second word lines; and
a peripheral circuit coupled to the memory array, and configured to:
apply a first bias voltage signal to the first word lines, apply a second bias voltage signal to the target word line, and apply a third bias voltage signal to the second word lines, during a pre-charge operation; and,
apply a program voltage signal to the target word line during a programming operation, wherein the programming operation comprises a first sub-programming operation and a second sub-programming operation, the memory array further includes memory cells, the first word line group comprises a first adjacent word line adjacent to the target word line, the second word line group comprises a second adjacent word line adjacent to the target word line, and the peripheral circuit is further configured to:
perform the first sub-programming operation on the memory cells coupled to the first adjacent word line;
perform the pre-charge operation, the first bias voltage signal, the second bias voltage signal, and the third bias voltage signal having a first set of set values;
perform the first sub-programming operation on the memory cells coupled to the target word line;
perform the first sub-programming operation on the memory cells coupled to the second adjacent word line;
perform the pre-charge operation, the first bias voltage signal, the second bias voltage signal, and the third bias voltage signal having a second set of set values; and,
perform the second sub-programming operation on the memory cells coupled to the target word line, the first set of set values being different from the second set of set values.

9. The memory according to claim 8 , wherein the peripheral circuit is further configured to control the first bias voltage signal, the second bias voltage signal, and the third bias voltage signal independently.

10. The memory according to claim 8 , wherein the first bias voltage signal has a first voltage value, the second bias voltage signal has a second voltage value, the third bias voltage signal has a third voltage value, and the first voltage value, the second voltage value, and the third voltage value are different from one another.

11. The memory according to claim 8 , wherein a voltage value of the first bias voltage signal is greater than a voltage value of the second bias voltage signal among the first set of set values, and a voltage value of the third bias voltage signal is greater than a voltage value of the second bias voltage signal among the second set of set values.

12. The memory according to claim 8 , wherein each of the memory cells is configured to be programmed to be in one of multi-level threshold states.

13. The memory according to claim 12 , wherein
the multi-level threshold states comprise at least a lowest-level threshold state and a highest-level threshold state, in the lowest-level threshold state the memory has a lowest-level minimum threshold voltage, in the highest-level threshold state the memory has a highest-level maximum threshold voltage, and there is a preset difference value between the highest-level maximum threshold voltage and the lowest-level minimum threshold voltage; and
the set values of the first bias voltage signal and the second bias voltage signal are related to the preset difference value, and the set values of the third bias voltage signal and the second bias voltage signal are related to the preset difference value.

14. The memory according to claim 8 , wherein
the memory cells coupled to each of the second word lines are in an erased state, the first bias voltage signal has a first voltage value, the second bias voltage signal has a second voltage value, and the third bias voltage signal has a third voltage value;
the first voltage value is great

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Qiu Lu
• Huang Xueqing
• Zhu Junyao
• Chen Yao

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C2211/5648

  Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title