Display substrate and display device

US12266307B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12266307-B2
Application numberUS-202318514197-A
CountryUS
Kind codeB2
Filing dateNov 20, 2023
Priority dateMay 6, 2020
Publication dateApr 1, 2025
Grant dateApr 1, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display substrate and a display device. The display substrate includes a base substrate and a plurality of sub-pixels on the base substrate, each sub-pixel includes a pixel circuit, and the pixel circuit includes a drive sub-circuit and a first reset sub-pixel. The first reset sub-pixel is configured to apply a first reset voltage to a control terminal of the drive sub-circuit in response to a first reset control voltage; the display substrate further comprises a first reset signal line electrically connected with the first terminal of the first reset sub-circuit to provide the first reset voltage, and the first reset signal line is in a semiconductor layer and comprises a doped semiconductor material.

First claim

Opening claim text (preview).

What is claimed is: 1. A display substrate, comprising: a base substrate; and a plurality of sub-pixels, arranged in a plurality of pixel rows along a first direction and a plurality of pixel columns along a second direction on the base substrate, wherein each of the plurality of sub-pixels comprises a pixel circuit, and the pixel circuit is configured to drive a light-emitting element corresponding to the each sub-pixel to emit light; the pixel circuit comprises a drive sub-circuit and a first reset sub-circuit; the drive sub-circuit comprises a control terminal, a first terminal, and a second terminal, and the drive sub-circuit is configured to be connected with the light-emitting element and control a drive current flowing through the light-emitting element; the first reset sub-circuit comprises a control terminal, a first terminal and a second terminal, the control terminal of the first reset sub-circuit is configured to receive a first reset control voltage, the first terminal of the first reset sub-circuit is configured to receive a first reset voltage, and the second terminal of the first reset sub-circuit is connected with the control terminal of the drive sub-circuit; the first rest sub-circuit is configured to apply the first reset voltage to the control terminal of the drive sub-circuit in response to the first reset control voltage; the display substrate further comprises a first reset signal line extended along the first direction, the first reset signal line is electrically connected with the first terminal of the first reset sub-circuit to provide the first reset voltage, and the first reset signal line is in a semiconductor layer and comprises a doped semiconductor material; the pixel circuit further comprises a second reset sub-circuit, and the second reset sub-circuit comprises a control terminal, a first terminal and a second terminal, the control terminal of the second reset sub-circuit is configured to receive a second reset control voltage, the first terminal of the second reset sub-circuit is configured to receive a second reset voltage, and the second terminal of the second reset sub-circuit is configured to be connected with the light emitting element; the pixel circuit further comprises a light emission control sub-circuit; the light emission control sub-circuit comprises a control terminal, a first terminal and a second terminal, the first terminal of the light emission control sub-circuit is connected with the second terminal of the drive sub-circuit, and the second terminal of the light emission control sub-circuit is configured to be connected with the light-emitting element; the second reset sub-circuit comprises a reset transistor comprising a gate electrode, a first electrode and a second electrode which respectively serve as the control terminal, the first terminal and the second terminal of the second reset sub-circuit, and the light emission control sub-circuit comprises a light emission control transistor comprising a gate electrode, a first electrode and a second electrode which respectively serve as the control terminal, the first terminal and the second terminal of the light emission control sub-circuit; the second electrode of the reset transistor and the second electrode of the light emission control transistor are both in the semiconductor layer and are spaced apart from each other, and are electrically connected with each other by a first connection electrode; and the first connection electrode is on a side of the semiconductor layer away from the base substrate. 2. The display substrate according to claim 1 , further comprising a second reset signal line extended along the second direction, wherein the second reset signal line is on a side of the first reset signal line away from the base substrate and is electrically connected with the first reset signal line; the second reset signal line and the first connection electrode are in a same layer and made of a same material. 3. The display substrate according to claim 1 , wherein the first connection electrode comprises a first connection terminal, a second connection terminal and a third connection terminal; the first connection terminal is electrically connected with the second terminal of the first reset sub-circuit, the second connection terminal is configured to be connected with the light-emitting element, and the third connection terminal is electrically connected with the second terminal of the light emission control sub-circuit. 4. The display substrate according to claim 3 , wherein the first connection electrode is in a U-shaped structure; and the first connection terminal and the second connection terminal are respectively at two end points of the U-shaped structure, and the third connection terminal is at a corner of the U-shaped structure close to the second connection terminal. 5. The display substrate according to claim 1 , further comprising a first reset voltage line extended along the first direction, wherein the first reset voltage line is electrically connected with the first terminal of the second reset sub-circuit to provide the second reset voltage, and the first reset voltage line is on a side of the first reset signal line away from the base substrate. 6. The display substrate according to claim 5 , further comprising a second connection electrode, wherein the second connection electrode is on a side of the first reset voltage line away from the base substrate and electrically connect the first terminal of the second reset sub-circuit and the first reset voltage line. 7. The display substrate according to claim 6 , wherein the pixel circuit further comprises a storage capacitor, wherein the storage capacitor comprises a first capacitor electrode and a second capacitor electrode, the first capacitor electrode is configured to receive a first power supply voltage, and the second capacitor electrode is electrically connected with the control terminal of the drive sub-circuit; and the first capacitor electrode and the first reset voltage line are in a same layer and insulated from each other, and the second capacitor electrode is on a side of the first capacitor electrode close to the base substrate. 8. The display substrate according to claim 1 , further comprising a first reset voltage terminal and a second reset voltage terminal which are insulated from each other, wherein the first reset voltage terminal is electrically connected with the first terminal of the first reset sub-circuit to provide the first reset voltage, and the second reset voltage terminal is electrically connected with the first terminal of the second reset sub-circuit to provide the second reset voltage. 9. The display substrate according to claim 8 , wherein the plurality of sub-pixels comprises a first sub-circuit and a second sub-pixel, and the first sub-pixel and the second sub-pixel correspond to light-emitting elements emitting different colors; the second reset voltage terminal is electrically connected with the first terminal of the second reset sub-circuit of the first sub-pixel to provide the second reset voltage to the first sub-pixel; the display substrate further comprises a third reset voltage terminal, and the third reset voltage terminal is electrically connected with the first terminal of the second reset sub-circuit of the second sub-pixel to provide the second reset voltage to the second sub-pixel. 10. The display substrate according to claim 9 , wherein the plurality of sub-pixels further comprise a third sub-pixel; the first sub-pixel, the second sub-pixel, and the third sub-pixel respectively correspond to a blue light-emitting element, a red light-emitting element, and a green light-e

Assignees

Inventors

Classifications

  • Arrangements or methods related to booting a display · CPC title

  • Preventing or counteracting the effects of ageing · CPC title

  • Details of timing specific for flat panels, other than clock recovery · CPC title

  • Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current · CPC title

  • with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

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What does patent US12266307B2 cover?
A display substrate and a display device. The display substrate includes a base substrate and a plurality of sub-pixels on the base substrate, each sub-pixel includes a pixel circuit, and the pixel circuit includes a drive sub-circuit and a first reset sub-pixel. The first reset sub-pixel is configured to apply a first reset voltage to a control terminal of the drive sub-circuit in response to …
Who is the assignee on this patent?
Chengdu Boe Optoelect Tech Co, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 01 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 11 related publications on this page (citations in our corpus or others sharing the same primary CPC).