Data structures, methods and tiling engines for storing tiling information in a graphics processing system

Patent metadata

Field	Value
Publication number	US-12266044-B2
Application number	US-202318401566-A
Country	US
Kind code	B2
Filing date	Dec 31, 2023
Priority date	Feb 10, 2020
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block. A tile is a valid tile for a primitive block if at least one primitive in the primitive block intersects that tile.

First claim

What is claimed is:

1. A method of tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles, the plurality of tiles being grouped into a plurality of tile groups each comprising at least two tiles, the method comprising, for a tile group:
determining, for each tile of the tile group, which primitives of each of a plurality of primitive blocks intersect that tile, each primitive block comprising at least one primitive; and
storing in memory a control stream, the control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of a control data block for the corresponding primitive block.

2. The method of claim 1 , wherein each primitive block entry comprises valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block, a tile being a valid tile for a primitive block if at least one primitive in the primitive block intersects that tile.

3. The method of claim 2 , wherein the valid tile information comprises a valid tile mask which comprises a bit for each tile in the tile group which indicates whether that tile is a valid tile for the primitive block.

4. The method of claim 2 , wherein the control stream comprises at least one other type of entry, each of the at least one other type of entry comprising valid tile information that indicates that none of the tiles of the tile group are valid tiles.

5. The method of claim 1 , wherein each control data block comprises information identifying which primitives of the corresponding primitive block intersect each tile of the tile group.

6. The method of claim 1 , wherein at least one control data block comprises at least one primitive mask which comprises a bit for each primitive in the corresponding primitive block that identifies whether or not that primitive intersects a set of one or more tiles of the tile group.

7. The method of claim 1 , wherein at least one control data block comprises a primitive mask for each tile of the tile group that intersects at least one primitive in the corresponding primitive block, each primitive mask comprising a bit for each primitive in the corresponding primitive block that identifies whether or not that primitive intersects the corresponding tile.

8. The method of claim 1 , wherein each control data block comprises information identifying an address of the corresponding primitive block in memory.

9. The method of claim 1 , wherein each control data block comprises a primitive block header that indicates: whether one or more of the tiles of the tile group intersect the same primitives of the corresponding primitive block and/or whether one or more of the tiles of the tile group intersect all of the primitives in the corresponding primitive block.

10. The method of claim 1 , wherein:
each primitive block entry comprises a data pointer that identifies the location in memory of the corresponding control data block;
the control stream comprises at least one control data base address entry which specifies at least a portion of a control data base address; and
an address of a control data block in memory is generated from a combination of the control data base address and the data pointer of the corresponding primitive block entry.

11. The method of claim 10 , wherein each data pointer comprises an offset into a portion of memory identified by the control data base address.

12. The method of claim 10 , wherein each control data base address entry specifies a complete control data base address.

13. The method of claim 10 , wherein each control data base address entry specifies only a portion of a complete control data base address.

14. The method of claim 13 , wherein the control stream comprises a first control data base address entry that specifies a first portion of the control data base address and a second control data base address entry that specifies a second portion of the control data base address.

15. The method of claim 1 , wherein storing the control stream in memory comprises dividing the control stream entries into a plurality of control stream blocks; wherein a last entry in each control stream block, other than the last control stream block, is a link entry which identifies a location of a next control stream block in memory.

16. The method of claim 1 , wherein each tile group comprises an N×M block of tiles in the render space wherein N and M are integers greater than or equal to 1.

17. The method of claim 1 , further comprising storing in memory the control data block for each primitive block that comprises at least one primitive that intersect at least one tile of the tile group.

18. A tiling engine for use in a graphics processing system for tiling primitives into tiles in a tile group of a rendering space, the tiling engine comprising:
tiling logic configured to determine, for each tile of the tile group, which primitives of each of a plurality of primitive blocks intersect that tile, each primitive block comprising at least one primitive; and
a control stream generator configured to store in memory a control stream, the control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of a control data block for the corresponding primitive block.

19. A non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to perform the method as set forth in claim 1 .

20. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of the tiling engine as set forth in claim 18 that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the tiling engine.

Assignees

• Imagination Tech Ltd

Inventors

• Yang Xile
• Brigg Robert
• Livesley Michael John

Classifications

• G06T2210/52

  Parallel processing · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06T15/00

  Three-dimensional [3D] image rendering · CPC title