Communicating data with stacked memory dies

Patent metadata

Field	Value
Publication number	US-12265489-B2
Application number	US-202318369622-A
Country	US
Kind code	B2
Filing date	Sep 18, 2023
Priority date	Oct 2, 2017
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

First claim

What is claimed is:

1. A method by a memory system, comprising:
receiving, at one or more components of the memory system, a first signal modulated using a first modulation scheme that includes only two levels;
generating, by the one or more components, a second signal comprising a first portion of bits of the first signal based at least in part on receiving the first signal;
generating, by the one or more components, a third signal comprising a second portion of bits of the first signal based at least in part on receiving the first signal;
generating, by the one or more components based at least in part on the second signal and the third signal, a fourth signal modulated using a second modulation scheme that includes three or more levels; and
transmitting, from the one or more components, the fourth signal.

2. The method of claim 1 , wherein generating the second signal is based at least in part on comparing the second signal with a reference signal.

3. The method of claim 2 , wherein generating the third signal is based at least in part on comparing the third signal with the reference signal.

4. The method of claim 1 , wherein generating the second signal comprises capturing bits on an edge of a first clock signal aligned with the first portion of bits, and generating the third signal comprises capturing bits on an edge of a second clock signal aligned with the second portion of bits.

5. The method of claim 1 , wherein generating the second signal comprises capturing bits on one of a rising edge or a falling edge of a clock signal aligned with the first portion of bits, and generating the third signal comprises capturing bits on the other of the rising edge or the falling edge of the clock signal aligned with the second portion of bits.

6. The method of claim 1 , further comprising:
deserializing the first signal after receiving the first signal, wherein generating the second signal is based at least in part on deserializing the first signal.

7. The method of claim 1 , wherein the fourth signal is transmitted to one or more memory dies of a plurality of memory dies.

8. The method of claim 1 , wherein the first signal is received from a host device.

9. A memory system, comprising:
a plurality of memory dies; and
one or more components coupled with the plurality of memory dies, the one or more components configured to:
receive a first signal modulated using a first modulation scheme that includes only two levels;
generate a second signal comprising a first portion of bits of the first signal based at least in part on receiving the first signal;
generate a third signal comprising a second portion of bits of the first signal based at least in part on receiving the first signal;
generate, based at least in part on the second signal and the third signal, a fourth signal modulated using a second modulation scheme that includes three or more levels; and
transmit the fourth signal.

10. The memory system of claim 9 , wherein the one or more components further comprise:
a deserializer configured to generate the second signal and generate the third signal;
a multiplexer configured to generate the fourth signal; and
a driver configured to transmit the fourth signal.

11. The memory system of claim 9 , wherein the one or more components are configured to generate the second signal based at least in part on comparing the second signal with a reference signal, and the one or more components are configured to generate the third signal based at least in part on comparing the third signal with the reference signal.

12. The memory system of claim 9 , wherein generating the second signal comprises capturing bits on an edge of a first clock signal aligned with the first portion of bits, and generating the third signal comprises capturing bits on an edge of a second clock signal aligned with the second portion of bits.

13. The memory system of claim 9 , wherein generating the second signal comprises capturing bits on one of a rising edge or a falling edge of a clock signal aligned with the first portion of bits, and generating the third signal comprises capturing bits on the other of the rising edge or the falling edge of the clock signal aligned with the second portion of bits.

14. The memory system of claim 9 , wherein the fourth signal has a serialization factor greater than 2 to 1.

15. The memory system of claim 9 , wherein the second signal excludes any bits of the second portion and the third signal excludes any bits of the first portion.

16. The memory system of claim 9 , wherein the fourth signal is transmitted to one or more memory dies of the plurality of memory dies.

17. The memory system of claim 9 , wherein the first signal is received from a host device.

18. A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more components of a memory system to:
receive, at the one or more components, a first signal modulated using a first modulation scheme that includes only two levels;
generate, by the one or more components, a second signal comprising a first portion of bits of the first signal based at least in part on receiving the first signal;
generate, by the one or more components, a third signal comprising a second portion of bits of the first signal based at least in part on receiving the first signal;
generate, by the one or more components based at least in part on the second signal and the third signal, a fourth signal modulated using a second modulation scheme that includes three or more levels; and
transmit, from the one or more components, the fourth signal.

19. The non-transitory computer-readable medium of claim 18 , wherein the fourth signal is transmitted to one or more memory dies of a plurality of memory dies.

20. The non-transitory computer-readable medium of claim 18 , wherein the first signal is received from a host device.

Assignees

• Lodestar Licensing Group Llc

Inventors

• Hasbun Robert Nasry
• Hollis Timothy M
• Wright Jeffrey P
• Gans Dean D

Classifications

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G06F13/4234

  being a memory bus · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title