Digital loop dual-stage source measure unit

Patent metadata

Field	Value
Publication number	US-12265115-B2
Application number	US-202318120933-A
Country	US
Kind code	B2
Filing date	Mar 13, 2023
Priority date	Mar 17, 2022
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

A dual-stage source measure unit (SMU) has a user interface to allow a user to input one or more target values, at least two terminals to couple to a device under test (DUT), a current loop having a current digital control loop (DCL), a current digital-to-analog converter (DAC), a sense resistor, a current analog-to digital converter (ADC), and a common ADC, the current DCL to receive inputs from the current ADC, from the common ADC, and a target value for the output current, and to control a first output stage to produce the output current, and a voltage loop having a voltage DCL, a voltage DAC, a voltage ADC, and the common ADC, the voltage DCL to receive inputs from the voltage ADC, from the common ADC, and a target value for the output voltage, and to control a second output stage to produce the output voltage.

First claim

I claim:

1. A dual-stage source measure unit (SMU), comprising:
a user interface to allow a user to input one or more target values;
at least two terminals configured to couple to a device under test (DUT);
a current loop comprising a current digital control loop (DCL), a current digital-to-analog converter (DAC), a sense resistor, a current analog-to digital converter (ADC), and a common ADC, the current DCL configured to receive inputs from the current ADC representing a value of an output current through the terminals, from the common ADC representing a value of a voltage of a common point, and a target value for the output current, and to control a first output stage by the current DAC to produce the output current; and
a voltage loop comprising a voltage DCL, a voltage DAC, a voltage ADC, and the common ADC, the voltage DCL configured to receive inputs from the voltage ADC representing a value of an output voltage across the terminals, from the common ADC representing the value of the voltage of the common point, and a target value for the output voltage, and to control a second output stage by the voltage DAC to produce the output voltage.

2. The dual-stage SMU as claimed in claim 1 , wherein, when the SMU is configured to source voltage, the current DCL is configured to control the first output stage to force the common point voltage to zero Volts and the voltage DCL is configured to control the second output stage to force a target output voltage across the terminals.

3. The dual-stage SMU as claimed in claim 1 , wherein, when the SMU is configured to source current, the current DCL is configured to control the first output stage to force a target output current through the DUT, and the voltage DCL is configured to control the second output stage to force the common point voltage to zero Volts.

4. The dual-stage SMU as claimed in claim 1 , wherein an input to the voltage ADC is driven by a signal representing a differential voltage between the at least two terminals.

5. The dual-stage SMU as claimed in claim 1 , wherein the first output stage output drives through the sense resistor to a first of the at least two terminals.

6. The dual-stage SMU as claimed in claim 1 , wherein an input to the current ADC is driven by a signal representing a differential voltage across the sense resistor.

7. The dual-stage SMU as claimed in claim 5 , wherein the second output stage drives a second of the at least two terminals.

8. The dual-stage SMU as claimed in claim 1 , wherein the at least two terminals comprise a first pair of terminals and a second pair of terminals, wherein the first pair of terminals are source terminals configured to couple to a pair of nodes of the DUT to convey the output current and output voltage to the DUT, and the second pair of terminals are sense terminals coupled to the voltage ADC and configured to couple to the pair of nodes of the DUT through connections that carry negligible current, and wherein the common point is located between the sense resistor and a first source terminal.

9. The dual-stage SMU as claimed in claim 8 , wherein the common point is located at the sense resistor.

10. The dual-stage SMU as claimed in claim 8 , where the common point is located at a first sense terminal.

11. The dual-stage SMU as claimed in claim 1 , wherein at least one target value has an upper value and a lower value.

12. The dual-stage SMU as claimed in claim 1 , wherein the voltage DCL regulates a function of values of the voltage ADC and values of the current ADC to the one or more target values.

13. The dual-stage SMU as claimed in claim 1 , wherein the current DCL regulates a function of values of the current ADC and values of the voltage ADC to the one or more target values.

14. The dual-stage SMU as claimed in claim 1 , wherein one of the one or more target values comprises a specified function of the current ADC and the voltage ADC and comprises one of resistance or power.

15. The dual-stage SMU as claimed in claim 1 , wherein one or both output stages have switchable variable gains.

16. The dual-stage SMU as claimed in claim 1 , wherein the sense resistor comprises a plurality of sense resistors switchable for sensing a wider range of current.

17. The dual-stage SMU as claimed in claim 1 , wherein one or both voltage sensing and current sensing have variable gains switchable for sensing a wider range of output voltage or output current.

18. A method of operating a source measure unit (SMU) having a voltage output stage coupled to terminals, and a current output stage coupled to a sense resistor, the method comprising:
receiving inputs comprising an input from a current analog-to-digital converter (ADC) representing a value of an output current, a common ADC representing a voltage of a common point, and a target value for the output current, and using a current digital-to-analog controller (DAC) to control a first output stage to produce the output current, when the SMU is sourcing current; and
receiving inputs comprising an input from a voltage ADC representing a value of an output voltage, the common ADC representing a voltage of the common point, and a target value for the output voltage, and using a voltage DAC to control a second output stage to produce the output voltage, when the SMU is sourcing voltage.

19. The method as claimed in claim 18 , further comprising controlling the first output stage to force the common point voltage to zero Volts, and forcing the target output voltage across the terminals, when the SMU is configured to source voltage.

20. The method as claimed in claim 18 , further comprising controlling the first output stage to force the target output current through the terminals, and controlling the second output stage to force the common point voltage to zero Volts, when the SMU is configured to source current.

Assignees

• Keithley Instruments

Inventors

• Goeke Wayne C

Classifications

• G01R31/2607

  Circuits therefor (G01R31/2642 takes precedence) · CPC title

• G01R19/0092

  Measuring current only · CPC title

• G01R31/31924

  Voltage or current aspects, e.g. driver, receiver · CPC title

• G01R19/2509

  Details concerning sampling, digitizing or waveform capturing · CPC title

• G01R31/2601 Primary

  Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title