Signal amplifying circuit and display device

Patent metadata

Field	Value
Publication number	US-12261575-B1
Application number	US-202318401542-A
Country	US
Kind code	B1
Filing date	Dec 31, 2023
Priority date	Nov 23, 2023
Publication date	Mar 25, 2025
Grant date	Mar 25, 2025

Abstract

The present application provides a signal amplifying circuit and a display device. In the signal amplifying circuit, a gate of a driving transistor of a first inverter is connected to an output terminal of a reset module, and thereby a potential of the gate of the driving transistor of the first inverter changes when an impedance of an optoelectronic device changes, so that a potential change of each node of the first inverter amplifies the signal. Besides, a first compensation transistor is connected between a second gate of the first driving transistor and a first output node, and the potential of the first output node precharges to the second gate of the first driving transistor to adjust a threshold voltage of the first driving transistor, thereby erasing the difference of the threshold voltages in different transistors, and solving the technical problem of bad uniformity of signals amplified by the inverter.

First claim

What is claimed is:

1. A signal amplifying circuit, comprising:
a reset module, wherein an input terminal of the reset module is connected to an input signal terminal;
an optoelectronic device, wherein a first terminal of the optoelectronic device is connected to an output terminal of the reset module, and a second terminal of the optoelectronic device is connected to the input signal terminal and the input terminal of the reset module;
a positive feedback module, wherein a first terminal of the positive feedback module is connected to a first constant voltage signal terminal, a second terminal of the positive feedback module is connected to a second constant voltage signal terminal, the positive feedback module at least comprises a first inverter, the first inverter comprises a first load transistor, a first driving transistor and a first output node, the first load transistor and the first driving transistor are connected to the first output node in the first inverter, the first output node is electrically connected to the output signal terminal, and a potential of the second constant voltage signal terminal is larger than a potential of the first constant voltage signal terminal;
wherein the first inverter further comprises a first compensation transistor, the first driving transistor comprises a first gate and a second gate, the first gate of the first driving transistor being connected to the output terminal of the reset module, a first electrode of the first compensation transistor being connected to the first output node, and a second electrode of the first compensation transistor being connected to the second gate of the first driving transistor.

2. The signal amplifying circuit of claim 1 , wherein the first inverter further comprises a first storage capacitor, a first plate of the first storage capacitor being connected to the second gate of the first driving transistor, and a second plate of the first storage capacitor being connected to the first constant voltage signal terminal.

3. The signal amplifying circuit of claim 1 , wherein the first load transistor comprises a first gate and a second gate, the first gate of the first load transistor being connected to a first electrode of the first load transistor, and the second gate of the first load transistor being connected to the first output node.

4. The signal amplifying circuit of claim 1 , wherein the positive feedback module further comprises a second inverter comprising a second load transistor, a second driving transistor, a second compensation transistor, and a second output node, a gate of the second load transistor is connected to the second constant voltage signal terminal, a first electrode of the second load transistor is connected to the second constant voltage signal terminal, a second electrode of the second load transistor and a first electrode of the second driving transistor are connected to the second output node, a gate of the first load transistor is connected to the second output node, and a second electrode of the second driving transistor is connected to the first constant voltage signal terminal;
wherein the second driving transistor comprises a first gate and a second gate, the first gate of the second driving transistor being connected to the first output node, a first electrode of the second compensation transistor being connected to the second output node, and a second electrode of the second compensation transistor being connected to the second gate of the second driving transistor.

5. The signal amplifying circuit of claim 1 , wherein the reset module comprises a reset transistor, a first electrode of the reset transistor being connected to the input signal terminal, a second electrode of the reset transistor being connected to the first terminal of the optoelectronic device, and a gate of the reset transistor being connected to a first scan signal line.

6. The signal amplifying circuit of claim 2 , wherein the reset module comprises a reset transistor, a first electrode of the reset transistor being connected to the input signal terminal, a second electrode of the reset transistor being connected to the first terminal of the optoelectronic device, and a gate of the reset transistor being connected to a first scan signal line.

7. The signal amplifying circuit of claim 3 , wherein the reset module comprises a reset transistor, a first electrode of the reset transistor being connected to the input signal terminal, a second electrode of the reset transistor being connected to the first terminal of the optoelectronic device, and a gate of the reset transistor being connected to a first scan signal line.

8. The signal amplifying circuit of claim 4 , wherein the reset module comprises a reset transistor, a first electrode of the reset transistor being connected to the input signal terminal, a second electrode of the reset transistor being connected to the first terminal of the optoelectronic device, and a gate of the reset transistor being connected to a first scan signal line.

9. The signal amplifying circuit of claim 5 , further comprising a voltage follower comprising a third load transistor, a third driving transistor, and a third output node, a gate of the third driving transistor being connected to the first output node, a first electrode of the third driving transistor being connected to the second constant voltage signal terminal, a second electrode of the third driving transistor and a first electrode of the third load transistor being connected to the third output node, a gate of the third load transistor being connected to a second scan signal line, and a second electrode of the third load transistor being connected to the first constant voltage signal terminal.

10. The signal amplifying circuit of claim 9 , wherein the third driving transistor comprises a first gate and a second gate, the first gate of the third driving transistor is connected to the first output node, and the second gate of the third driving transistor is connected to the third output node; and
the third load transistor comprises a first gate connected to the second scan signal line and a second gate connected to the first constant voltage signal terminal.

11. The signal amplifying circuit of claim 9 , further comprising an addressing module comprising an addressing transistor, a first electrode of the addressing transistor being connected to the third output node, a gate of the addressing transistor being connected to a third scan signal line, and a second electrode of the addressing transistor being connected to the output signal terminal.

12. The signal amplifying circuit of claim 11 , wherein the reset transistor comprises a first gate and a second gate, the first gate of the reset transistor is connected to the first scan signal line, and the second gate of the reset transistor is connected to a fourth scan signal line;
the first compensation transistor comprises a first gate and a second gate, the first gate of the first compensation transistor is connected to the first scan signal line, and the second gate of the first compensation transistor is connected to the fourth scan signal line; and
the addressing transistor comprises a first gate connected to the third scan signal line and a second gate connected to the fourth scan signal line.

13. A display device comprising a plurality of pixel units, at least one of the pixel units comprising a signal amplifying circuit and a pixel circuit, the signal amplifying circuit comprising:
a reset module, wherein an input terminal of the reset module is connected to an input signal terminal;
an optoelectronic device, wherein a first terminal of the optoele

Assignees

• Tcl China Star Optoelectronics Tech Co Ltd

Inventors

• Zhou Zhichao
• Tan Zhiwei

Classifications

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/36

  using liquid crystals · CPC title

• G09G3/3225

  using an active matrix · CPC title

• H03F3/08

  controlled by light · CPC title