Using renamed registers to support multiple vset{i}vl{i} instructions

Patent metadata

Field	Value
Publication number	US-12260217-B2
Application number	US-202318115970-A
Country	US
Kind code	B2
Filing date	Mar 1, 2023
Priority date	Dec 2, 2022
Publication date	Mar 25, 2025
Grant date	Mar 25, 2025

Abstract

A method for renaming architectural register, such as control and status register (CSR), is disclosed. The method includes decoding an instruction for updating CSR, updating the CSR based on a respective instruction of the one or more instructions, allocating a unique tag to the instruction in pipeline, and writing the tag into a mapping table for renaming the CSR. The tag can identify the CSR included in the instruction or the updated values of the CSR. The tag can be associated with a unique value. Moreover, the method can employ a First In, First Out (FIFO) queuing technique and virtual bits.

First claim

What is claimed is:

1. A method for renaming architectural register, comprising:
decoding one or more instructions in a pipeline, wherein the one or more instructions update a control and status register (CSR), wherein the one or more instructions are of a same type, and the CSR includes a first register and a second register;
updating values in the CSR based on a respective instruction of the one or more instructions;
allocating one or more tags to the respective instruction in the pipeline,
wherein the one or more tags identify the CSR included in or associated with the one or more instructions or the updated values of the CSR, and
wherein each of the one or more tags is associated with a unique value; and

writing, for renaming the CSR, values of the first register and the second register into a mapping table as one combined unit such that the values of the first register and the second register are reduced to a single entry.

2. The method of claim 1 , wherein the first register is a vector type register (vtype) and the second register is a vector length register (vl).

3. The method of claim 2 , further comprising:
when a respective instruction of the one or more instructions that overwrote a respective tag retires from the pipeline, liberating the respective tag.

4. The method of claim 3 , wherein the respective tag is liberated in an order that is different from an allocated order.

5. The method of claim 3 , further comprising:
wherein the respective tag is liberated in a program order.

6. A method for renaming architectural register, comprising:
decoding one or more instructions in a pipeline, wherein the one or more instructions update a control and status register (CSR) including a vector type register (vtype) and vector length register (vl);
allocating, based on the one or more instructions, a register entry of the CSR into a first in, first out (FIFO) queue;
updating the register entry based on a respective instruction of the one or more instructions; and
deallocating, when the respective instruction of the one or more instructions retire from the pipeline, the register entry.

7. The method of claim 6 , wherein the allocating is managed by an allocation pointer that points to a next register entry to be allocated.

8. The method of claim 6 , wherein the deallocating is managed by a retirement pointer to point to a next register entry to be retired.

9. The method of claim 8 , further comprising:
allocating, using a virtual bit, a virtual index to the FIFO queue.

10. The method of claim 6 , further comprising:
writing an updated value of an updated register entry to an integer register file.

11. A non-transitory computer readable medium comprising a circuit representation that, when processed by a computer, is used to program or manufacture an integrated circuit comprising:
a processor including circuitry configured to:
decode one or more instructions in a pipeline, wherein the one or more instructions update a control and status register (CSR), wherein the one or more instructions are of a same type, and the CSR includes a first register and a second register;
update values in the CSR;
allocate one or more tags to the respective instruction in pipeline,
wherein the one or more tags identify the CSR included in or associated with the one or more instructions or the updated values of the CSR, and
wherein each of the one or more tags is associated with a unique value; and

writing, for renaming the CSR, values of the first register and the second register into a mapping table as one combined unit such that the values of the first register and the second register are reduced to a single entry.

12. The non-transitory computer readable medium of claim 11 , wherein the first register is a vector type register (vtype) and the second register is a vector length register (vl).

13. The non-transitory computer readable medium of claim 12 , wherein the processor including circuitry is further configured to:
when a respective instruction of one or more instructions that overwrote a respective tag retires from the pipeline, liberate the respective tag.

14. The non-transitory computer readable medium of claim 13 , wherein the respective tag is liberated in an order that is different from an allocated order.

15. The non-transitory computer readable medium of claim 13 , wherein the respective tag is liberated in a program order.

16. The non-transitory computer readable medium of claim 13 , wherein:
an entry of the CSR is held in a first in, first out (FIFO) queue before the values of the CSR is updated; and
the processor including circuitry is further configured to allocate, using a virtual bit, a virtual index to the FIFO queue.

Assignees

• Sifive Inc

Inventors

• Smith Josh

Classifications

• G06F9/3856

  Reordering of instructions, e.g. using queues or age tags · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/384

  Register renaming · CPC title

• G06F9/30101 Primary

  Special purpose registers · CPC title