Systems, methods, and apparatuses for matrix add, subtract, and multiply

Patent metadata

Field	Value
Publication number	US-12260213-B2
Application number	US-202117548214-A
Country	US
Kind code	B2
Filing date	Dec 10, 2021
Priority date	Mar 20, 2017
Publication date	Mar 25, 2025
Grant date	Mar 25, 2025

Abstract

Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.

First claim

We claim:

1. A processor comprising:
decode circuitry to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier, wherein each of the first source matrix operand, the second source matrix operand, and the destination matrix operand corresponds to a two-dimensional matrix of values; and
execution circuitry to execute the decoded instruction to, for each data element position of the identified first source matrix operand:
multiply a first data value at that data element position by a second data value at a corresponding data element position of the identified second source matrix operand, and
store a result of the multiplication into a corresponding data element position of the identified destination matrix operand;

wherein a fault is generated when the first source matrix operand has a different number of data elements than the second source matrix operand.

2. The processor of claim 1 , wherein the first source matrix operand is a packed data register and the second source matrix operand is a memory location.

3. The processor of claim 1 , wherein the first source matrix operand is a packed data register and the second source matrix operand is a packed data register.

4. The processor of claim 1 , wherein the execution circuitry comprises a plurality of fused-multiply adders.

5. The processor of claim 1 , wherein the opcode indicates that each of the first source matrix operand, the second source matrix operand, and the destination matrix operand comprises half-precision floating-point values.

6. The processor of claim 1 , wherein the opcode indicates that each of the first source matrix operand, the second source matrix operand, and the destination matrix operand comprises single-precision floating-point values.

7. The processor of claim 1 , wherein a fault is generated when a number of rows associated with the first source matrix operand is different than a number of rows associated with the second source matrix operand.

8. The processor of claim 1 , wherein a fault is generated when a number of columns associated with the first source matrix operand is different than a number of columns associated with the second source matrix operand.

9. A method comprising:
decoding an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier, wherein each of the first source matrix operand, the second source matrix operand, and the destination matrix operand corresponds to a two-dimensional matrix of values; and
executing the decoded instruction to, for each data element position of the identified first source matrix operand:
multiply a first data value at that data element position by a second data value at a corresponding data element position of the identified second source matrix operand, and
store a result of the multiplication into a corresponding data element position of the identified destination matrix operand;
wherein a fault is generated when the first source matrix operand has a different number of data elements than the second source matrix operand.

10. The method of claim 9 , wherein the first source matrix operand is a packed data register and the second source matrix operand is a memory location.

11. The method of claim 9 , wherein the first source matrix operand is a packed data register and the second source matrix operand is a packed data register.

12. The method of claim 9 , wherein the opcode indicates that each of the first source matrix operand, the second source matrix operand, and the destination matrix operand comprises half-precision floating-point values.

13. The method of claim 9 , wherein the opcode indicates that each of the first source matrix operand, the second source matrix operand, and the destination matrix operand comprises single-precision floating-point values.

14. The method of claim 9 , wherein a fault is generated when a number of rows associated with the first source matrix operand is different than a number of rows associated with the second source matrix operand.

15. The method of claim 9 , wherein a fault is generated when a number of columns associated with the first source matrix operand is different than a number of columns associated with the second source matrix operand.

16. A non-transitory machine-readable medium storing an instruction which when executed by a processor causes the processor to perform a method, the method comprising:
decoding an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier, wherein each of the first source matrix operand, the second source matrix operand, and the destination matrix operand corresponds to a two-dimensional matrix of values, and
executing the decoded instruction to, for each data element position of the identified first source matrix operand:
multiply a first data value at that data element position by a second data value at a corresponding data element position of the identified second source matrix operand, and
store a result of the multiplication into a corresponding data element position of the identified destination matrix operand;
wherein a fault is generated when the first source matrix operand has a different number of data elements than the second source matrix operand.

17. The non-transitory machine-readable medium of claim 16 , wherein the first source matrix operand is a packed data register and the second source matrix operand is a memory location.

18. The non-transitory machine-readable medium of claim 16 , wherein the first source matrix operand is a packed data register and the second source matrix operand is a packed data register.

Assignees

• Intel Corp

Inventors

• Valentine Robert
• Baum Dan
• Sperber Zeev
• Corbal Jesus
• Ould-Ahmed-Vall Elmoustapha
• Toll Bret L
• Charney Mark J
• Ziv Barukh
• Heinecke Alexander
• Girkar Milind
• Rubanovich Simon

Classifications

• G06F2212/455

  Image or video data · CPC title

• G06F2212/454

  Vector or matrix data · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F12/0207

  with multidimensional access, e.g. row/column, matrix · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title