DRAM-based LIDAR pixel

Patent metadata

Field	Value
Publication number	US-12259498-B2
Application number	US-202117155871-A
Country	US
Kind code	B2
Filing date	Jan 22, 2021
Priority date	Jan 27, 2020
Publication date	Mar 25, 2025
Grant date	Mar 25, 2025

Abstract

A Light Detection and Ranging (LIDAR) detector circuit includes a memory device comprising a non-transitory storage medium that is configured to store data indicative of detection events in respective memory bins, and at least one control circuit. The at least one control circuit is configured to receive detection signals from one or more photodetector elements, identify a presence or an absence of detection events indicated by the detection signals during a portion of time between pulses of an emitter signal output from a LIDAR emitter element, and execute one of a first memory operation or a second memory operation to update the data in the respective memory bins responsive to identification of the presence or the absence of the detection events, respectively. Related circuits and methods of operation are also discussed.

First claim

The invention claimed is:

1. A Light Detection and Ranging (LIDAR) detector circuit, comprising:
a memory device comprising a non-transitory storage medium that is configured to store histogram data in respective memory bins; and
at least one control circuit configured to:
receive detection signals from one or more photodetector elements;
execute a first memory operation to update the histogram data in the respective memory bins responsive to the detection signals indicating a presence of detection events during a portion of time between pulses of an emitter signal output from a LIDAR emitter element, wherein the first memory operation comprises an increment operation; and
execute a second memory operation to update the histogram data in the respective memory bins responsive to the detection signals indicating an absence of the detection events during the portion of the time between the pulses of the emitter signal, wherein the second memory operation comprises a refresh operation, and

wherein the increment operation or the refresh operation to update the histogram data stored in the respective memory bins of the memory device is completed within the time between the pulses of the emitter signal.

2. The LIDAR detector circuit of claim 1 , wherein the at least one control circuit is configured to execute the refresh operation at a frequency that is greater than or less than a frequency of the pulses of the emitter signal, and wherein the frequency of the refresh operation is temperature-dependent.

3. The LIDAR detector circuit of claim 1 , wherein the at least one control circuit comprises a logic-based counter circuit that is configured to perform the increment operation or the refresh operation.

4. The LIDAR detector circuit of claim 3 , wherein the counter circuit comprises a plurality of serially-connected adder circuits.

5. The LIDAR detector circuit of claim 3 , wherein the counter circuit comprises a linear feedback shift register that is configured to execute the increment operation by shifting bits stored in the respective memory bins forward using a linear feedback loop.

6. The LIDAR detector circuit of claim 5 , wherein the linear feedback shift register is configured to execute the refresh operation by feeding bits stored in the respective memory bins back to at least one input thereof.

7. The LIDAR detector circuit of claim 1 , wherein the increment or refresh operations are performed sequentially for the respective memory bins.

8. The LIDAR detector circuit of claim 7 , wherein the memory device is a memory array comprising respective rows or columns of dynamic random access memory (DRAM) cells that define the respective memory bins, and wherein at least one control circuit is further configured to output a readout signal responsive to a read signal that is sequentially applied to the respective rows or columns.

9. The LIDAR detector circuit of claim 8 , wherein the memory device and the one or more photodetector elements comprise the DRAM cells and a plurality of the photodetector elements that are native to a same wafer, or are provided on respective wafers and electrically interconnected.

10. The LIDAR detector circuit of claim 8 , wherein the DRAM cells are provided in respective trenches between the photodetector elements and define optical and/or electrical barriers between adjacent ones of the photodetector elements.

11. The LIDAR detector circuit of claim 8 , wherein the readout signal comprises a count signal and/or a time integration signal, and wherein the at least one control circuit is configured to calculate an estimated time of arrival of photons incident on the photodetector elements based on the readout signal.

12. The LIDAR detector circuit of claim 1 , wherein the portion of the time between the pulses of the emitter signal corresponds to a respective distance subrange, and wherein the respective memory bins comprise histogram data corresponding to the respective distance subrange.

13. The LIDAR detector circuit of claim 12 , wherein the photodetector elements comprise single-photon avalanche detectors (SPADs), and wherein the histogram data comprises photon counts indicated by the detection signals corresponding to the respective distance subrange.

14. The LIDAR detector circuit of claim 1 , wherein the at least one control circuit is configured to transmit respective strobe signals that activate the one or more photodetector elements for respective detection windows that are differently delayed between the pulses of the emitter signal.

15. The LIDAR detector circuit of claim 14 , wherein the respective detection windows correspond to respective distance subranges, and wherein the at least one control circuit is configured to transmit the respective strobe signals to activate the one or more photodetector elements to sequentially cycle through the respective distance subranges.

16. A Light Detection and Ranging (LIDAR) detector circuit, comprising:
one or more photodetector elements defining a LIDAR detector pixel;
a memory device comprising a non-transitory storage medium that is configured to store data in respective memory bins, wherein the memory bins comprise dynamic random access memory (DRAM) cells; and
at least one processor circuit configured to receive detection signals from the one or more photodetector elements, identify an absence of detection events indicated by the detection signals during a portion of time between pulses of an emitter signal output from a LIDAR emitter element, and execute a memory operation to update the data in the respective memory bins responsive to identification of the absence of the detection events,
wherein the DRAM cells are provided in respective trenches between the photodetector elements and define optical and/or electrical barriers between adjacent ones of the photodetector elements.

17. The LIDAR detector circuit of claim 16 , wherein the memory operation is a refresh operation, and wherein the at least one processor circuit is further configured to identify a presence of the detection events indicated by the detection signals during the portion of the time between the pulses of the emitter signal, and execute an increment operation to update the data in the respective memory bins responsive to identification of the presence of the detection events.

18. The LIDAR detector circuit of claim 17 , wherein the at least one processor circuit is configured to execute the refresh operation at a frequency that is greater than or less than a frequency of the pulses of the emitter signal, optionally and wherein the frequency of the refresh operation is temperature-dependent.

19. The LIDAR detector circuit of claim 18 , wherein the at least one processor circuit comprises a linear feedback shift register that is configured to execute the increment operation by shifting bits stored in the respective memory bins forward using a linear feedback loop, and is configured to execute the refresh operation by feeding bits stored in the respective memory bins back to at least one input thereof.

20. The LIDAR detector circuit of claim 17 , wherein the increment operation or the refresh operation to update the data stored in the respective memory bins of the memory device is completed within the time between the pulses of the emitter signal.

21. The LIDAR detector circuit of claim 17 , wherein the portion of the time between the pulses of the emitter signal correspond to a respective distance subrange, the respective memory bins comprise histogra

Assignees

• Sense Photonics Inc

Inventors

• Henderson Robert
• Finkelstein Hod

Classifications

• H04N25/773

  comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD] · CPC title

• G01S7/4915

  Time delay measurement, e.g. operational details for pixel components (signal extraction and conditioning G01S7/493); Phase measurement · CPC title

• G01S7/4817 Primary

  relating to scanning · CPC title

• G01S7/484

  Transmitters · CPC title

• G01S17/931

  of land vehicles · CPC title